Abstract: In one embodiment, a method is provided. The method comprises upon entering a self-refresh mode, refreshing memory cells in a memory device at a first refresh frequency; and upon a predefined event refreshing the memory cells at a second refresh frequency, while in the self-refresh mode.

Abstract: A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: A thermal management system is described which may be implemented on a semiconductor die. The system may include a thermal sensor thermally coupled to the die to sense the temperature of the die and generate an output representing the sensed temperature, and an adjustable compensation circuit coupled to the thermal sensor to compensate the thermal sensor output. The adjustable compensation circuit may be applied to the thermal sensor or to a threshold.

Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Abstract: Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

Abstract: Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Abstract: Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

Abstract: A codec in a processor-based system handles at least two separate audio programs at the same time. This may be useful, for example, for simultaneously playing one audio program while recording another audio program. A first digital to analog converter pair may be coupled to a first mixer and a second digital to analog converter pair may include a second mixer. Thus, two separate audio programs may be handled at the same time, each by a separate digital to analog converter and mixer.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.

Abstract: Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.

Abstract: A scheme to facilitate deterministic thermal management by having either device connected via a link to generate a thermal management request based on one device's thermal capability and the present conditions. The request is transmitted over the link to the other device with a specific sleep period. Consequently, the receiving device responds with an acknowledgement within a pre-configured or pre-agreed response time.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: Systems and methods of power management provide for controlling the idleness of a processor based on an operating system schedule. The idleness of at least one device is synchronized with the idleness of the processor. Idleness synchronization may involve deferring bus transactions, suspending memory refresh, turning off power to clock sources and turning off power to combinatorial logic during an idle window in the OS schedule.

Abstract: In one embodiment, a method includes periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if the capacitor has discharged before the timer has counted down to zero then generating an interrupt.

Abstract: Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.