Patents by Inventor Aniruddha Konar
Aniruddha Konar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10164027Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: October 26, 2017Date of Patent: December 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 10163716Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: October 25, 2017Date of Patent: December 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20180130655Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: October 25, 2017Publication date: May 10, 2018Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9911598Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: January 12, 2017Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20180053828Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: October 26, 2017Publication date: February 22, 2018Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9876084Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: March 29, 2016Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9705079Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: November 4, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20170194467Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: January 12, 2017Publication date: July 6, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9680096Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: July 15, 2016Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9647210Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: March 23, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9613867Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: March 29, 2016Date of Patent: April 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20170062234Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: March 29, 2016Publication date: March 2, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Publication number: 20170062594Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: March 29, 2016Publication date: March 2, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Publication number: 20170047515Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: November 4, 2016Publication date: February 16, 2017Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9508930Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: April 19, 2016Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160315254Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: July 15, 2016Publication date: October 27, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160284995Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: April 19, 2016Publication date: September 29, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160284870Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9419016Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: GrantFiled: November 10, 2014Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9419115Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: GrantFiled: October 6, 2015Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V. R. M. Murali, Edward J. Nowak