Patents by Inventor Aniruddha Konar

Aniruddha Konar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Symmetric tunnel field effect transistor
    Patent number: 9379253
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL
    Publication number: 20160133648
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V.R.M. Murali, Edward J. Nowak
  • JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL
    Publication number: 20160133730
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.
    Type: Application
    Filed: October 6, 2015
    Publication date: May 12, 2016
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V.R.M. Murali, Edward J. Nowak