Abstract: A method, system, and product are disclosed for determining an inductance of an entire integrated circuit package taken as a whole. A model is generated of the entire integrated circuit package which has a first port, a second port, and a third port. The first port of the model is coupled in parallel to an energy source and a resistor having a known resistance. The second port of the model is shorted. And, the third port of the model is opened. The package is simulated by exciting the first port utilizing the energy source and measuring a voltage at the first port in order to produce a waveform. A time constant is determined utilizing the waveform. The inductance of the entire integrated circuit package is then determined from the first port with respect to the second port using the known resistance and the time constant.

Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.

Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.

Abstract: An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.

Abstract: An optimal buffer is chosen for insertion at a node by calculating a &pgr;-model of a downstream circuit to a child node where the &pgr;-model contains at least a capacitance value. The gate delay is computed at the node using an effective capacitance derived from the &pgr;-model and buffer characteristics of a particular buffer. The interconnect delay is then computed from sets of moments associated with each gate downstream from the node via a bottom-up incremental technique. Slack is computed using the gate delay for the child node and the interconnect delay for the child node and then the computed slack is compared to the slack of other buffers at the node. The node may be a sink or have one or two children.

Abstract: Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.

Abstract: A method for optimal insertion of buffers into an integrated circuit design. A model representative of a plurality of circuits is created where each circuit has a receiving node coupled to a conductor and a source. A receiving node is selected from the modeled plurality of circuits and circuit noise is calculated for the selected receiving node utilizing the circuit model. If the calculated circuit noise exceeds an acceptable value an optimum distance is computed from the receiving node on the conductor for buffer insertion. In a multi-sink circuit merging of the noise calculation for the two receiving circuits must be accomplished. If an intersection of conductors exists between the receiving node and the optimum distance a set of candidate buffer locations is generated. The method then prunes inferior solutions to provide an optimal insertion of buffers.

Abstract: A method and system for segmenting wires in the design stage of a integrated circuit to allow for the efficient insertion of an optimum quantity of buffers. The method begins by locating wires in the integrated circuit which interconnect transistors and then determining the characteristics of the transistor and the characteristics of the interconnecting wires. Next, the method computes a first upper limit for an optimum quantity of buffers utilizing total capacitive load wire and transistor characteristics, then the method computes a second upper limit for an optimum quantity of buffers assuming buffer insertion has decoupled the capacitive load. Finally, the method segments the wires by inserting nodes utilizing the greater of the first computation or the second computation. A determined upper limit on buffer quantity allows wires to be segmented such that the number of candidate buffer insertion topologies is manageable.

Abstract: An efficient method for identifying potential noise failures in an integrated circuit design by predicting peak noise within a victim circuit of an integrated circuit. Initially, a victim circuit within an integrated circuit is located. An aggressor circuit within the integrated circuit is located which has a physical relationship with the victim circuit, normally proximity. The slope of a signal within the aggressor circuit is analyzed and the coupling currents induced in the victim circuit by the aggressor circuit are computed. The input slope of the aggressor circuit and the physical relationship between the victim circuit and the aggressor circuit are utilized to determine a peak current induced into the victim circuit utilizing modelled coupling capacitance. The peak current and the equivalent impedance of the victim circuit can be utilized to determine peak noise. Noise failures on integrated circuits can be avoided by detecting peak noise which is above acceptable levels.