Patents by Inventor Anirudh

Anirudh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754645
    Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 5, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Anirudh Amarnath, Tai-Yuan Tseng
  • Patent number: 9746895
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 29, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 9748765
    Abstract: This document describes techniques and apparatuses of load allocation for multi-battery devices. In some embodiments, these techniques and apparatuses determine an amount of load power that a multi-battery device consumes to operate. Respective efficiencies at which the device's multiple batteries are capable of providing power are also determined. A respective portion of load power is then drawn from each of the batteries based on their respective efficiencies.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 29, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bojun Huang, Thomas Moscibroda, Ranveer Chandra, Stephen E. Hodges, Julia L. Meinershagen, Nissanka Arachchige Bodhi Priyantha, Anirudh Badam, Pan Hu, Anthony John Ferrese, Evangelia Skiani
  • Publication number: 20170245191
    Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for recovering from media degradation during a communication session. In a particular embodiment, a method provides, during a communication session between a first user system operated by a first user and a second user system operated by a second user, receiving a first indication from the first user system indicating a degraded condition of media received by the first user system from the second user system. Responsive to receiving the indication, the method provides attempting to establish a connection with a third user system associated with the second user when the degraded condition comprises inactivity of the media being received by the first user system from the second user system. Upon establishing the connection with the third user system, the method provides connecting the third user system to the first user system to continue the communication session.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 24, 2017
    Inventors: Anirudh Patel, Manish Patil, Parag Mulay
  • Patent number: 9740234
    Abstract: An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 22, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Kim, Paul Policke, Anirudh Kadiyala
  • Publication number: 20170228246
    Abstract: Techniques are provided for reducing the amount of data that to be transferred in a hybridcloud system in order to spawn a VM at a private cloud computing system from a template library stored in a public cloud computing system. Instead of storing full virtual machine templates, template libraries at the public cloud computing system are “differential” libraries. Differential templates in these differential libraries only include data that is different as compared with either a base template or another differential template. Assuming a private cloud system already stores a base image, the private cloud system may spawn a VM based on a particular template simply by downloading the appropriate differential templates. This technique reduces the total amount of data that needs to be downloaded from the public cloud system in order to spawn a particular VM.
    Type: Application
    Filed: March 29, 2016
    Publication date: August 10, 2017
    Inventors: VENU GOPALA RAO KOTHA, SHASHIDHAR NARAYANA KRISHNAMURTHY, ANIRUDH AGARWAL, SURESHBABU KOYADAN CHATHOTH
  • Patent number: 9728241
    Abstract: Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 8, 2017
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Swaroop Ghosh, Anirudh Srikant Iyengar, Jae-Won Jang
  • Patent number: 9727723
    Abstract: Techniques to reduce false positives in detecting anomalous use of resources are disclosed. In various embodiments, resource access data indicating for each resource in a set of resources respective usage data for each of one or more users of the resource is received. Cluster analysis is performed to determine one or more clusters of users. For each cluster, a set of recommended resources to be associated with the cluster is determined. For each of at least a subset of users, a temporal behavior based model for each user that reflects one or more resources included in the set of recommended resources associated with a corresponding cluster of which the user is a member is generated.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: August 8, 2017
    Assignee: EMC IP Holding Co. LLC
    Inventors: Anirudh Kondaveeti, Derek Lin, Hulya Emir-Farinas
  • Publication number: 20170221173
    Abstract: A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Anirudh Rajendra Acharya, Alexei Vladimirovich Bourd, David Rigel Garcia Garcia, Milind Nilkanth Nemlekar, Vineet Goel
  • Publication number: 20170223392
    Abstract: Architecture that enables the identification of entities such as people and content in live broadcasts (e.g., streaming content (e.g., video) of live events) and non-live presentations (e.g., movies), in realtime, using recognition processes. This can be accomplished by extracting live data related to a live event. With respect to people entities, filtering can be performed to identify the named (people) entities from the extracted live data, and trending topics discovered as relate to the named entities, as associated with the live event. Multiple images of the named entities that capture the named entities under different conditions are captured for the named entities. The images are then processed to extract and learn facial features (train one or more models), and facial recognition is then performed on faces in the video using the trained model(s).
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Anirudh Koul, Serge-Eric Tremblay
  • Patent number: 9720717
    Abstract: Techniques are disclosed relating to enabling virtual machines to access data on a physical recording medium. In one embodiment, a computing system provides a logical address space for a storage device to an allocation agent that is executable to allocate the logical address space to a plurality of virtual machines having access to the storage device. In such an embodiment, the logical address space is larger than a physical address space of the storage device. The computing system may then process a storage request from one of the plurality of virtual machines. In some embodiments, the allocation agent is a hypervisor executing on the computing system. In some embodiments, the computing system tracks utilizations of the storage device by the plurality of virtual machines, and based on the utilizations, enforces a quality of service level associated with one or more of the plurality of virtual machines.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 1, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Neil Carson, Nisha Talagala, Mark Brinicombe, Robert Wipfel, Anirudh Badam, David Nellans
  • Publication number: 20170212573
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Publication number: 20170212568
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Publication number: 20170214476
    Abstract: A method and apparatus are provided for calculating s-parameters of a device under test from step waveforms acquired by a time domain network analyzer.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Peter J. Pupalaikis, Kaviyesh B. Doshi, Anirudh K. Sureka
  • Publication number: 20170201440
    Abstract: A request to subscribe to QoS information is received from a monitoring element. A monitoring element may be a centralized communication system, such as a Private Branch Exchange (PBX). The QoS information is from a plurality of network elements at a plurality of locations. A network element may be, for example, a communication endpoint, a router, a media server, and/or the like. The QoS information is based on a location map that includes information for the plurality of locations. The plurality of locations are controlled by separate communication systems. A determination is made whether a threshold for the QoS information has been reached. If the threshold for the QoS information has reach reached, a notification is sent to the monitoring element. Upon receiving the notification, the monitoring element can cause an action to occur to address a QoS problem.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: Vivek Joshi, Anirudh Patel, Manish Patil
  • Publication number: 20170199852
    Abstract: Techniques are described for populating visual designs with web content. In implementations, a document design is generated via a digital media application. The document design includes a layout of repeating design elements, such as a grid or table of repeating areas each having various design elements. Web content having a structured arrangement of data elements is accessed through a data panel exposed via the application. The web content data may be linked to the document design to populate elements of the document design with “real-world” data. To do so, the web content is to detect semantically similar repeating data elements by based on element positions, node types, style types, and node hierarchies reflected by structured data defining the web content. Design elements in the layout of the document design are then auto-populated with content of the semantically similar repeating data elements to produce a preview linked to “real-world” data.
    Type: Application
    Filed: March 9, 2016
    Publication date: July 13, 2017
    Inventor: Anirudh Sasikumar
  • Publication number: 20170199851
    Abstract: Techniques are described for populating visual designs with web content. In implementations, a document design is generated via a digital media application. The document design includes a layout of repeating design elements, such as a grid or table of repeating areas each having various design elements. Web content having a structured arrangement of data elements is accessed through a data panel exposed via the application. The web content data may be linked to the document design to populate elements of the document design with “real-world” data. To do so, the web content is to detect semantically similar repeating data elements by based on element positions, node types, style types, and node hierarchies reflected by structured data defining the web content. Design elements in the layout of the document design are then auto-populated with content of the semantically similar repeating data elements to produce a preview linked to “real-world” data.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 13, 2017
    Inventor: Anirudh Sasikumar
  • Patent number: 9704020
    Abstract: Architecture that enables the identification of entities such as people and content in live broadcasts (e.g., streaming content (e.g., video) of live events) and non-live presentations (e.g., movies), in realtime, using recognition processes. This can be accomplished by extracting live data related to a live event. With respect to people entities, filtering can be performed to identify the named (people) entities from the extracted live data, and trending topics discovered as relate to the named entities, as associated with the live event. Multiple images of the named entities that capture the named entities under different conditions are captured for the named entities. The images are then processed to extract and learn facial features (train one or more models), and facial recognition is then performed on faces in the video using the trained model(s).
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 11, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Anirudh Koul, Serge-Eric Tremblay
  • Patent number: 9696782
    Abstract: This document describes techniques and apparatuses for suppressing power spikes. In some embodiments, these techniques and apparatuses determine an available amount of power that a battery is capable of providing while maintaining a particular voltage level and a requisite amount of power that components will consume to perform a task. When the requisite amount of power exceeds the available amount of power, power states of the components are altered effective to enable the battery to maintain the particular voltage level.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 4, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ranveer Chandra, Stephen E. Hodges, Julia L. Meinershagen, Nissanka Arachchige Bodhi Priyantha, Anirudh Badam, Thomas Moscibroda, Pan Hu, Anthony John Ferrese, Evangelia Skiani
  • Publication number: 20170169243
    Abstract: One or more systems and/or techniques are provided for managing a partially encrypted file system, for storage hardware virtualization, and/or for storage management. In example, data may be stored in a partially encrypted file system, where sensitive data is encrypted for security and non-sensitive data is unencrypted, which may mitigate energy usage otherwise used for encrypting non-sensitive data, thus improving battery life. In an example, a storage device may be exposed to applications as a plurality of isolated storage structures where an application is provided data access to an isolated storage structure assigned to the application but not to isolated storage structures assigned to other applications, which may provide hardware level isolation with improved energy efficiency. In an example, a storage management component, configured to provide isolation and encryption, may be integrated into a computing device as an application specific integrated circuit (ASIC) or a system on a chip (SoC).
    Type: Application
    Filed: January 31, 2017
    Publication date: June 15, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Anirudh Badam, Ranveer Chandra, Qi Zhang, Bruce Lee Worthington, Jing Li