Abstract: Apparatus and method for constructing a cartilage structure preferably has a first plate, and a blade mounted over the first plate. The blade preferably has (i) a predetermined shape, and (ii) a cutting edge protruding from the first plate and configured to cut a cartilage into the predetermined shape. A second plate preferably has a guide imprint adjacent a surface thereof, the guide imprint having a shape complimentary to the predetermined shape of the blade. A press preferably has (i) a first surface configured to mount the first plate, and (ii) a second surface configured to mount the second plate. Actuation structure is preferably configured to press together the press first and second surfaces to thereby cause the blade to cut the cartilage in the predetermined shape. The method utilizes similar structure to prepare at least two cartilages, which are joined together to form a three-dimensional cartilage structure.

Abstract: A method for isolating analytics logic from content creation is a rich Internet application. In an embodiment, a method for isolating analytics tracking logic comprises receiving a rich Internet application, identifying a plurality of event elements within the content separate from content creation, tagging the identified plurality of event elements, wherein the event elements are tagged in isolation of content creation, and storing the content including the tagged event elements. The set of tagged event elements may be modified in isolation of content creation.

Abstract: A shared electrode battery includes multiple electrodes of one type (e.g., two or more cathodes) that share an electrode of another type (e.g., a shared anode). The multiple electrodes of the same type (e.g., the multiple cathodes) can have different characteristics, such as different chemistries, particle sizes and distributions, capacities, and so forth that are designed to provide particular features such as high energy density, high power density, high cycle life, fast charge, safety, and so forth. Multiple cathode-anode pairings of one of the multiple electrodes of the same type with the shared electrode are possible. Switching hardware is operable to select one of the multiple pairings at any given time, allowing the battery to provide power using the cathode having the desired characteristics at that given time. A single battery is thus able to provide these multiple different features.

Abstract: Architecture that enables the identification of entities such as people and content in live broadcasts (e.g., streaming content (e.g., video) of live events) and non-live presentations (e.g., movies), in realtime, using recognition processes. This can be accomplished by extracting live data related to a live event. With respect to people entities, filtering can be performed to identify the named (people) entities from the extracted live data, and trending topics discovered as relate to the named entities, as associated with the live event. Multiple images of the named entities that capture the named entities under different conditions are captured for the named entities. The images are then processed to extract and learn facial features (train one or more models), and facial recognition is then performed on faces in the video using the trained model(s).

Abstract: Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The functionality then allows processes (or other entities) to interact with the information unit via the shared virtual memory resources, as opposed to duplicating separate private instances of the virtual memory resources for each process that requests access to the information unit. The functionality also uses a single level of address translation to convert virtual addresses to corresponding physical addresses. In one implementation, the information unit is stored on a bulk-erase type block storage device, such as a flash storage device; here, the single level of address translation incorporates any address mappings identified by wear-leveling and/or garbage collection processing, eliminating the need for the storage device to perform separate and independent address mappings.

Abstract: Latency-based selections of energy storage devices are described herein. In implementations, latency behavior of computing tasks performed by a computing device is predicted for a period of time. Based on the predicted latency behavior of the computing device over the period of time, an assessment is made regarding which of multiple heterogeneous energy storage devices are most appropriate to service the system workload. For example, high energy density devices may be favored for latency sensitive tasks whereas high energy density devices may be favored when latency sensitivity is not a concern. A combination of energy storage devices to service the current workload is selected based upon the latency considerations and then power supply settings are adjusted to cause supply of power from the selected combination of energy storage devices during the time period.

Abstract: Schedule-based energy storage device selection is described for a device having an energy storage device system with heterogeneous energy storage devices, such as heterogeneous battery cells. The techniques discussed herein use information regarding a user's schedule (e.g., the user's calendar) to predict future workload patterns for a computing device and reserve energy storage device capacities across multiple heterogeneous energy storage devices to improve efficiency of the energy storage devices. For example, if a user is expected to attend a video conference call later in the day (e.g., due to the video conference call being on the user's calendar), then energy in an energy storage device that is better capable of handling such a workload (providing power during the video conference call) more efficiently is preserved so that the energy is available when the video conference call occurs.

Abstract: Systems and methods for fabricating three-dimensional objects. The system includes an optical imaging system providing a light source; a photosensitive medium adapted to change states upon exposure to a portion of the light source from the optical imaging system; a control system for controlling movement of the optical imaging system, wherein the optical imaging system moves continuously above the photosensitive medium. The method includes moving a maskless optical imaging system providing the light beam in a continuous sequence; presenting the light beam on a portion of the photosensitive medium; lowering a plate upon which the photosensitive medium resides; and applying a new layer of the photosensitive medium.

Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.

Abstract: A method of data processing, the method comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream marker, the at least one command stream marker indicating a workload type of the command stream, determining, by the GPU, an operation algorithm for the GPU based on the at least one command stream marker prior to executing the command stream, and executing, by the GPU, the command stream based on the operation algorithm.

Abstract: A multiple energy storage device fuel gauge is described for a device having a power system with multiple heterogeneous energy storage devices. The fuel gauge keeps track of a present state of multiple heterogeneous energy storage devices simultaneously. The fuel gauge implements collective measurement of voltage and current of the multiple heterogeneous energy storage devices via shared circuitry to determine status information, such as state of charge (SOC) and internal resistance values. A controller of the fuel gauge uses various measurements and energy storage device-specific parameters to compute status values indicative of the state of each energy storage device. The status values are maintained by the fuel gauge and exposed to other system components to facilitate power management decisions. A communication bus is used to communicate between the fuel gauge and system components, and a software API may be exposed to facilitate access to various energy storage device specific information.

Abstract: A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more operations in the command stream in a trace buffer, wherein the first set of one or more operations accesses one or more memory locations in memory, and wherein the data include an indication of contents of the one or more memory locations associated with the first set of one or more operations. The command processor may interrupt the processing of the command stream. The command processor may, in response to resuming processing of the command stream subsequent to the interrupting of the processing of the command stream, replay at least a portion of the command stream, including processing a second set of one or more operations of the command stream based at least in part on the data stored in the trace buffer.

Abstract: Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The functionality then allows processes (or other entities) to interact with the information unit via the shared virtual memory resources, as opposed to duplicating separate private instances of the virtual memory resources for each process that requests access to the information unit. The functionality also uses a single level of address translation to convert virtual addresses to corresponding physical addresses. In one implementation, the information unit is stored on a bulk-erase type block storage device, such as a flash storage device; here, the single level of address translation incorporates any address mappings identified by wear-leveling and/or garbage collection processing, eliminating the need for the storage device to perform separate and independent address mappings.

Abstract: Multiple tenants within a hybrid cloud computing system may need IP addresses to communicate over a computer network external to the hybrid cloud system (such as the Internet). IP addresses are a scarce resource, and each address can only be assigned to a single tenant. With multiple tenants competing for IP addresses, many request collisions may occur if tenants request IP addresses in a naive manner, such as by requesting the next available IP address numerically. When a collision occurs, a tenant must request a different IP address. Instead, tenants request random IP addresses within a particular subnet in a random manner, thereby reducing the number of collisions that occur and improving the latency associated with requesting an IP address.

Abstract: A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

Abstract: A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.

Abstract: This disclosure describes techniques for context switching. In one example, a graphics processing unit may be configured to generate one or more signatures for context information stored in on-chip memory of the graphics processing unit, determine whether the one or more signatures match any previously generated signatures for context information stored in one or more memories accessible by the graphics processing unit, store, to at least one of the one or more memories, any signature of the one or more signatures that is determined not to match any previously generated signature stored in at least one of the one or more memories, and store, to at least one of the one or more memories, the context information respectively corresponding to the one or more signatures determined not to match any previously generated signature stored in at least one of the one or more memories.

Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.

Abstract: One or more systems and/or techniques are provided for managing a partially encrypted file system, for storage hardware virtualization, and/or for storage management. In example, data may be stored in a partially encrypted file system, where sensitive data is encrypted for security and non-sensitive data is unencrypted, which may mitigate energy usage otherwise used for encrypting non-sensitive data, thus improving battery life. In an example, a storage device may be exposed to applications as a plurality of isolated storage structures where an application is provided data access to an isolated storage structure assigned to the application but not to isolated storage structures assigned to other applications, which may provide hardware level isolation with improved energy efficiency. In an example, a storage management component, configured to provide isolation and encryption, may be integrated into a computing device as an application specific integrated circuit (ASIC) or a system on a chip (SoC).