Patents by Inventor Anirudh

Anirudh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060203581
    Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 14, 2006
    Inventors: Rajiv Joshi, Anirudh Devgan
  • Publication number: 20060195502
    Abstract: A method, computer program, and apparatus for compensating for group delay. The method comprises the steps of generating a raw step response of a system, differentiating the raw step response to generate an impulse response of the system, windowing the impulse response and taking a Fast Fourier Transform (FFT) of the windowed impulse response to generate a frequency response of the system. A phase response of the system is then calculated from the frequency response, and an IFFT Group Delay filter is defined in accordance with the phase response of the system. Finally, the IFFT Group Delay filter is applied to the raw step response.
    Type: Application
    Filed: November 1, 2005
    Publication date: August 31, 2006
    Applicant: LeCroy Corporation
    Inventors: Anirudh Sureka, Peter Pupalaikis
  • Publication number: 20060171129
    Abstract: An assembly includes a circuit board with a ball grid array device attached to a first side of the circuit board. A brace surrounding the ball grid array device has a series of mounting holes and a series of members extending between the mounting holes. The brace is removably secured to the first side of the circuit board at the mounting holes.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 3, 2006
    Inventors: Thomas Berto, Anirudh Vaze
  • Patent number: 7036104
    Abstract: A method of and system for optimizing a tree to meet timing constraints inserts buffers at selected ones of the internal nodes of a tree to form a plurality of subtrees. The method sizes the wires of the subtrees according to a wire code for each subtree, wherein each wire of a subtree has the same wire code. The buffers are inserted and the wires are sized such that slack along the path from a single source node to each sink node of the tree is equal to or greater than zero.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: April 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Steven Thomas Quay, Anirudh Devgan
  • Patent number: 7021795
    Abstract: Illumination apparatus (8) which comprises at least two light sources, at least one light collecting device for collecting light from the light sources (10), motion providing means for providing relative motion between the light sources (10) and the light collecting device (14), and control means for controlling the illumination of the light sources (10) such that the light sources (10) are illuminated for a predetermined time period when in a predetermined position relative to the light collecting device (14).
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: April 4, 2006
    Assignee: SEOS Limited
    Inventors: Nicholas Richard Coates, Anirudh Luthra
  • Publication number: 20060053185
    Abstract: A method and apparatus for generating a reflection filter. The method comprises the steps of determining an averaged step response of an acquired signal and generating a spectrum response from the averaged step response. A time at which a reflection in the averaged step response begins is determined and information in the averaged step response after the determined time when the reflection begins is replaced with an ideal flat line response to generate a required step response. A spectrum response is generated from the required step response and each frequency point of the spectrum response corresponding to the required step response is divided by each frequency point of the spectrum response corresponding to the averaged step response to generate a spectrum of the reflection filter. The result of the dividing step is processed to generate a reflection filter impulse response.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 9, 2006
    Inventor: Anirudh Sureka
  • Patent number: 7000205
    Abstract: A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anirudh Devgan, Chandramouli V. Kashyap
  • Patent number: 6985272
    Abstract: Image display apparatus comprising projector means, optical means for splitting incident light, a first modulator for modulating red light, a second modulator for modulating green light, a third modulator for modulating blue light, optical means for recombining the combined modulated red light, green light and blue light, and control means for controlling the operation of the first, second, third and fourth modulators such that the dynamic range of the image display apparatus is enhanced.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: January 10, 2006
    Assignee: SEOS Limited
    Inventors: Raymond John Bridgwater, Anirudh Luthra, John Robert Harding, Geoffrey Howard Blackham, Ian MacPherson
  • Patent number: 6968306
    Abstract: A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceff is computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceff is characterized by: Ceff=Cfj(1?e?T/?dj) where Cfj is the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and ?dj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap
  • Patent number: 6950996
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Publication number: 20050166227
    Abstract: In a terrestrial broadcast system, a program manager filters program data via a first tuner while a second tuner receives one of audio or video information of a channel from a transport stream. The program data is then parsed for channel information. The channel information is stored in a database.
    Type: Application
    Filed: January 27, 2004
    Publication date: July 28, 2005
    Applicant: PIONEER RESEARCH CENTER USA, INC.
    Inventor: Anirudh JOSHI
  • Publication number: 20050138584
    Abstract: A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Michael Beattie, Anirudh Devgan, Byron Krauter, Hui Zheng
  • Patent number: 6868533
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: March 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Publication number: 20050044515
    Abstract: An integrated circuit design has circuit macros made up of device cells. The cells are characterized by determining the leakage current dependency on various process, environmental and voltage parameters. When circuit macros are designed their leakage power is calculated using this data and multi-dimensional models for power and temperature distribution. Circuit macros are identified as timing-critical and timing-noncritical macros. Statistical methods are used to determine the average leakage sensitivities for the specific circuit macros designed. The designer uses the sensitivity data to determine how to redesign selected circuit macros to reduce leakage power. Reducing leakage power in these selected circuits may be used to reduce overall IC power or the improved power margins may be used in timing-critical circuits to increase performance while keeping power dissipation unchanged.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 24, 2005
    Applicant: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Sani Nassif
  • Patent number: 6842714
    Abstract: A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Ying Liu, Sani R. Nassif, Haihua Su
  • Publication number: 20040243955
    Abstract: A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu
  • Publication number: 20040243954
    Abstract: A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Applicant: International Business Machines Corporation
    Inventors: Anirudh Devgan, Chandramouli V. Kashyap
  • Publication number: 20040198306
    Abstract: This invention relates to a system for disabling a cellphone in the presence of certain conditions, and for switching it off in the presence of some other conditions, while allowing its use in the normal fashion in the absence of these two sets of conditions. Thus, this system regulates cellphone use in accordance with specified restrictions in specific locations, and allows its normal functioning when these restrictions are not required. Specifically, a first condition is an attempt to operate a cellphone by the driver of a vehicle having its ignition on and/or moving above a certain speed. In such a condition the system would automatically disable the OK switch of a cellphone and may also perform the CALL END function. In the second condition the system automatically switches off any cellphone in the ON condition being carried on the person of an individual occupying a seat in an aircraft, or a committee room, or any other such location where such a restriction is envisaged.
    Type: Application
    Filed: March 25, 2004
    Publication date: October 7, 2004
    Inventors: Yash Pal Singh, Anirudh Singh, Manu Singh, Lakinder Singh Verma
  • Publication number: 20040176939
    Abstract: A method, system, and product are disclosed for determining an inductance of an entire integrated circuit package taken as a whole. A model is generated of the entire integrated circuit package which has a first port, a second port, and a third port. The first port of the model is coupled in parallel to an energy source and a resistor having a known resistance. The second port of the model is shorted. And, the third port of the model is opened. The package is simulated by exciting the first port utilizing the energy source and measuring a voltage at the first port in order to produce a waveform. A time constant is determined utilizing the waveform. The inductance of the entire integrated circuit package is then determined from the first port with respect to the second port using the known resistance and the time constant.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Applicant: International Business Machines Corporation
    Inventors: Michael Werner Beattie, Anirudh Devgan, Byron Lee Krauter
  • Publication number: 20040169823
    Abstract: Image display apparatus comprising projector means, optical means for splitting incident light, a first modulator for modulating red light, a second modulator for modulating green light, a third modulator for modulating blue light, optical means for recombining the combined modulated red light, green light and blue light, and control means for controlling the operation of the first, second, third and fourth modulators such that the dynamic range of the image display apparatus is enhanced.
    Type: Application
    Filed: November 26, 2003
    Publication date: September 2, 2004
    Inventors: Raymond John Bridgwater, Anirudh Luthra, John Robert Harding, Geoffrey Howard Blackham, Ian MacPherson