Abstract: A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.

Abstract: A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.

Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.

Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.

Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.

Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.

Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

Abstract: A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.

Abstract: A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked.