Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.

Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Abstract: A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked.

Abstract: An integrated circuit including a substrate, multiple devices, and voltage control devices. The devices may include high threshold, low threshold, and standard threshold voltage devices. The devices and the voltage control devices are distributed across and coupled to the same substrate. Each voltage control device is configured to apply a back bias voltage at one of multiple discrete offset voltage levels. At least one voltage control device applies a first offset voltage level for back biasing high threshold voltage devices and at least one voltage control device applies a second offset voltage level for back biasing low threshold voltage devices. The selection of back biasing is based on relative population density of the different types of devices and varies across the substrate. Fine grain reverse back biasing reduces leakage current while reducing any performance decrease. Fine grain forward back biasing improves performance while reducing any leakage current increase.

Abstract: The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.

Abstract: The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.

Abstract: An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.

Abstract: An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.

Abstract: A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.

Abstract: A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.

Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

Abstract: A method of error correction includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a second operational phase, the raw data is outputted from the bus interface device to the bus master. In addition, error correction data is calculated, and error correction is performed on the raw data during the second operational phase. By retrieving the raw data before performing error correction, and by outputting the raw data during the same operational phase, data may be retrieved from the memory more rapidly.

Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.