Patents by Inventor Anisul H. Khan

Anisul H. Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040077178
    Abstract: A method for laterally etching a structure on a semiconductor substrate comprising depositing a protective mask that thins towards a bottom of the structure and lateral etching a wall of the structure to form a notch or to release the structure.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 22, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Chan-Syun Yang, Anisul H. Khan, Ajay Kumar, Padmapani C. Nallan
  • Publication number: 20040033697
    Abstract: A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 19, 2004
    Applicants: Applied Materials, Inc., Infineon Technologies
    Inventors: Ajay Kumar, Anisul H. Khan, Dragan Podlesnik, Sharma V. Pamarthy, Axel Henke, Stephan Wege, Virinder Grewal
  • Publication number: 20030222296
    Abstract: A method of forming a capacitor using a high dielectric constant material.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 4, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Ajay Kumar, Padmapani Nallan, Anisul H. Khan, Ralph Kerns, Virinder S. Grewal
  • Publication number: 20030211753
    Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Padmapani C. Nallan, Ajay Kumar, Anisul H. Khan, Chan-Syun David Yang