Abstract: A user-to-entity communication channel is established for providing increased information regarding entities to the general population. Ambassadors for a entity are identified and selected based on location history of devices for which location reporting is authorized. The ambassadors may provide information regarding the entity to the public through the communication channel. Communications between the users and ambassadors may be reported to the entity owner for analysis by the entity owner.

Abstract: Event workflow management in computing systems are disclosed herein. In one example, a process includes receiving a data package defining an event containing data representing a category corresponding to a type of activity of the event and having a workflow property. The process can then include creating or modifying a backend workflow of the event corresponding to the workflow property of the category and monitoring for the one or more status conditions of the event included in the backend workflow. When the monitoring indicates that the one or more status conditions of the event are satisfied, the one or more actions in the sequence of the backend workflow are executed in relation to the event.

Abstract: A user-to-entity communication channel is established for providing increased information regarding entities to the general population. Ambassadors for a entity are identified and selected based on location history of devices for which location reporting is authorized. The ambassadors may provide information regarding the entity to the public through the communication channel. Communications between the users and ambassadors may be reported to the entity owner for analysis by the entity owner.

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

Abstract: A method for repairing a memory device with faulty memory cells. The method includes defining a RA environment comprising a location of each of the faulty memory cells and a plurality of SR and a plurality of SC. The method further includes repairing the faulty memory cells based on an RA training process using the defined RA environment and mapping of the location of each faulty memory cell with the plurality of SC or SR. The method further includes training, based on a determination that indicates the at least one faulty memory cell among the faulty memory cells is left unrepaired and the at least one SC or SR is remaining, a first NN to perform an action for repairing of the faulty memory cells such that a maximum number of faulty memory cells are reparable and a minimum number of SC and SR are utilized during the repairing.

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Abstract: The disclosed embodiments provide a system for managing data conflation. During operation, the system generates matches between a first set of entities in a first dataset from a first data provider and a second set of entities in a second dataset from a second data provider based on comparisons of fields in the first and second datasets. Next, the system modifies a join query for joining the first and second datasets to include operators representing compliance rules for the first or second datasets. The system executes the modified join query to produce a joined dataset that adheres to the compliance rules and stores data related to the joined dataset within a platform that logically isolates the data from additional datasets. During processing of queries of the data, the system modifies the queries to include additional operators that enforce access control policies for the data.

Abstract: Aspects of the technology evaluate places that are familiar to a given user in order to provide contextualized location information about other places of interest. This may include evaluating the actual number of visits by the given user to one or more locations in a given geographical area. For instance, places that have been visited a sufficient number of times within a particular timeframe are identified as personal landmarks for that user. Thus, when the user searches for a specific place or otherwise requests results that fit a query, the system can use the personalized landmark information to help rank search results and to provide location cues to aid the user to quickly and efficiently arrive at the location of the search result. Personal landmarks are necessarily familiar to the user, and thus can reduce the number of turn-by-turn directions or simplify the graphical interface of the client device.

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

Abstract: Techniques for a flexible data security and machine learning system for merging third-party data are provided. In one technique, the system receives a data set from a third-party entity and receives selection data that indicates that the third-party entity selected a set of data security policies that includes an encryption option and a data mixing option from among multiple data mixing options. In response to receiving the selection data, the system stores data that associates the set of data security policies with the data set, encrypts the data set according to the encryption option, and persistently stores the encrypted data set. Later, the system decrypts the encrypted data set in volatile memory, generates, based on the data mixing option, training data based on the decrypted version of the data set, trains a machine-learned model based on the training data, and stores the machine-learned model in association with the data set.

Abstract: The present disclosure describes a method and system for generating at least one pattern from at least one data set using quantum computing. The system comprises at least one quantum processor; and at least one non-quantum processor operatively coupled to the at least one quantum processor and configured to process the at least one data set to generate at least one first intermediary pattern comprising at least one first keyword and transmit the generated pattern(s) to the quantum processor(s). The quantum processor(s) is configured to receive the data set(s) and the first intermediary pattern(s); process the data set(s) to generate at least one second intermediary pattern and at least one corresponding metadata; and process the first intermediary pattern(s) and the at least one second intermediary pattern(s) to generate the at least one final pattern.

Abstract: A device may receive a request to migrate source data, associated with a source platform, to a target platform. The device may select a target template associated with the target platform based on the request; obtain target information based on the target template; and generate a target mapping based on the source data and the target information. The device may analyze the target mapping to identify an unmapped element in the target mapping and determine, using a migration analysis model, a candidate mapping, for the unmapped element, between a set of the source data and a target element of the target elements. The device may provide a notification that identifies the candidate mapping, to permit a user selection associated with verifying the candidate mapping. The device may receive the user selection and migrate the source data to the target platform according to the target mapping and the user selection.

Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Abstract: The present disclose includes, among other things, compounds that inhibit CDK9, pharmaceutical compositions and methods of making and using the same.

Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Abstract: A device receives network data associated with a network that includes network devices interconnected by links, wherein the network devices utilize segment routing. The device receives segment routing data associated with the network, wherein the segment routing data at least includes a list of segments associated with paths provided through the network by two or more of the network devices and corresponding links. The device merges the network data and the segment routing data to generate merged data, and processes the merged data, with an optimization model, to determine potential network plans within a particular time period. The device identifies a potential network plan, of the potential network plans, that maximizes throughput associated with operating the network, and performs one or more actions based on the potential network plan.

Abstract: Aspects of the present disclosure provide systems, methods, and computer-readable storage media that support automated optimization of product management systems. In embodiments, automated optimization of component tools of the product management system is provided by automated evaluation and optimization of associated rules and metadata. In embodiments, metadata and rules may be associated to each other by an assessment engine. A recommendation engine may then identify non-compliant metadata, may determine a condition of the rule, and/or may generate recommendations for the rules based on the non-compliant metadata. Automated optimization of the product management system may include automated creation and mapping of decomposition relationships between commercial products and technical products. In embodiments, input data may be parsed into a set of object with unique attribute fields, which may then be validated.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for data associated with a deleted file to be recovered from the memory when the data is overwritten by a new file at the same logical address. To locate the data, the controller may identify a logical address associated with the data based on a directory entry associated with a FAT. The controller may determine a physical location of the data associated with the logical address based on one or more control entries in a L2P mapping table, such as a previous control entry in the table. The controller may also determine the physical location based on a hot count associated with the previous control entry. After the physical location is determined, the controller may associate a new logical address with the physical location of the data to recover the deleted file.