Abstract: Embodiments of the present disclosure provide techniques for low power design. A low power digital circuit system may include a high speed digital circuit. A first supply voltage may be applied to the high speed digital circuit. The digital circuit system may include a circuit stack that includes a first low speed digital circuit and a second low speed digital circuit stacked vertically on top relative to the first low speed digital circuit. Each of the first low speed digital circuit and the second low speed digital circuit may be configured for being driven at a second supply voltage that is less than the first supply voltage, and may be connected at a central node with a node voltage that is substantially same as the second supply voltage. The digital circuit system may include a load balancing circuit and one or more level shifter components.

Abstract: A sigma-delta (??) analog to digital converter (ADC) circuit receives an analog signal and outputs a pulse density modulated digital signal. A digital filter filters a sequence of data values for the pulse density modulated digital signal. The digital filter includes a multi-stage delay line, an encoder circuit configured to encode data values of the sequence of data values for input to the multi-stage delay line, and decoder circuits configured to decode data values output from corresponding taps of the multi-stage delay line. The encoder may be a Binary to Gray code encoder and the decoder may be a Gray to Binary code decoder.

Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

Abstract: Pulses having a first width and a second width greater than the first width are generated from a clock signal. An encoded data stream transmitted over a single communications wire is generated by: selecting the pulse having the first width for each bit of the transmit serial data stream having a first logic state; and selecting the pulse having the second width for each bit of the transmit serial data stream having a second logic state. Pulses of the received encoded data stream having the second width are then detected. A first flip-flop logic state is toggled in response to each detected pulse having the second width. A second flip-flop latches the first flip-flop logic state in response to each pulse of the encoded data stream. Outputs of the first and second flip-flops are logically combined to generate a receive serial data stream corresponding to the transmit serial data stream.

Abstract: Provided is a circuit having a first input configured receive first data, a second input coupled configured to receive second data, a clock input configured to receive a clock signal during a first time period, the clock signal having a triggering edge during the first time period and an output. The circuit is configured to, before the first time period commences, output the first data over the output and in response to receiving the clock signal having the triggering edge during the first time period, output the second data over the output and refrain from outputting the first data.

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may reduce direct current (DC) bias in biased signal inputs. For example, an example system includes a signal operator and an adaptive filter. The signal operator receives a biased signal input. The adaptive filter provides an estimated bias parameter to the signal operator. The signal operator generates an unbiased signal output based at least in part on the biased signal input and the estimated bias parameter.

Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.

Abstract: A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.

Abstract: Provided is a filter that includes a plurality of filter stages that are serially coupled. Each filter stage of the plurality of filter stages includes a plurality of latches. The plurality of latches are respectively driven by a plurality of clock signals. The plurality of clock signals are different from each other. Each filter stage includes a flip flop coupled to a last latch of the plurality of latches. The flip flop and the last latch are driven by a first clock signal of the plurality of clock signals.

Abstract: Offset calibration for an analog front-end system is provided. The analog front-end system includes a variable-gain amplifier, and the calibration mitigates an offset error of the variable-gain amplifier. Calibration is based on a difference-based estimation technique combined with digital iteration. Difference-based estimation includes measuring different digital output signals from an analog-to-digital converter for different respective gains of the variable-gain amplifier. The digital iteration is utilized to estimate offsets values which converge a digital output difference to a target of zero volts.

Abstract: In accordance with various embodiments of the present disclosure, a circuit to adjust a loop division factor (LDF) of a phase locked loop (PLL) is provided. In some embodiments, the circuit comprises processing circuitry configured to (1) determine an amount of jitter of a received input frequency comprising a plurality of input ticks, the amount of jitter being an amount of variation between an expected receipt of each of the plurality of input ticks and an actual receipt thereof, (2) determine a moving average of the determined amount of jitter, (3) determine an adjusted LDF based on the determined moving average of the determined amount of jitter, and (4) output the adjusted LDF to a PLL.

Abstract: Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

Abstract: An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N?1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

Abstract: Various embodiments of the present disclosure disclose improved BIST systems and methods for testing digital devices. A method for testing a digital device includes receiving, based at least in part on an input signal, an output signal from a device under testing (DUT). The output signal is processed to generate a noise signal and a recovered signal for the DUT. The controller may generate a signal to noise power ratio based at least in part on the noise and recovered signals and compare the signal to noise power ratio to a predetermined power threshold to generate a performance metric.