Patents by Inventor Ankur Bal
Ankur Bal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10218380Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.Type: GrantFiled: July 16, 2018Date of Patent: February 26, 2019Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh
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Patent number: 10211850Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.Type: GrantFiled: July 13, 2018Date of Patent: February 19, 2019Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh
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Patent number: 10050640Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.Type: GrantFiled: January 8, 2018Date of Patent: August 14, 2018Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh
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Patent number: 10050607Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.Type: GrantFiled: December 17, 2014Date of Patent: August 14, 2018Assignee: STMicroelectronics International N.V.Inventors: Neha Bhargava, Ankur Bal
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Patent number: 10050606Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.Type: GrantFiled: June 23, 2017Date of Patent: August 14, 2018Assignee: STMicroelectronics International N.V.Inventors: Neha Bhargava, Ankur Bal
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Patent number: 9858913Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: GrantFiled: May 15, 2017Date of Patent: January 2, 2018Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida
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Publication number: 20170294898Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.Type: ApplicationFiled: June 23, 2017Publication date: October 12, 2017Inventors: Neha Bhargava, Ankur Bal
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Patent number: 9780803Abstract: A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (??) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.Type: GrantFiled: September 15, 2016Date of Patent: October 3, 2017Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Chandrajit Debnath, Neha Bhargava
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Publication number: 20170249931Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida
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Patent number: 9685150Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: GrantFiled: May 6, 2014Date of Patent: June 20, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida
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Patent number: 9379728Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.Type: GrantFiled: June 26, 2015Date of Patent: June 28, 2016Assignee: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Shiva Sharath Babu Kaleru, Ankur Bal, Mohit Singh, Rakesh Malik
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Publication number: 20160182014Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Neha Bhargava, Ankur Bal
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Patent number: 9246509Abstract: A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.Type: GrantFiled: September 2, 2014Date of Patent: January 26, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Neha Bhargava, Ankur Bal
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Patent number: 9225321Abstract: Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.Type: GrantFiled: June 29, 2011Date of Patent: December 29, 2015Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Anupam Jain
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Patent number: 9015219Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.Type: GrantFiled: May 10, 2012Date of Patent: April 21, 2015Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Anupam Jain, Neha Bhargava
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Patent number: 8878710Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.Type: GrantFiled: November 15, 2012Date of Patent: November 4, 2014Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Neha Bhargava, Anupam Jain
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Publication number: 20140241539Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: ApplicationFiled: May 6, 2014Publication date: August 28, 2014Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Anupam JAIN, Rakhel Kumar PARIDA
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Patent number: 8803718Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.Type: GrantFiled: March 16, 2012Date of Patent: August 12, 2014Assignee: STMicroelectronics International N.V.Inventors: Rakhel Kumar Parida, Ankur Bal, Anil Kumar, Anupam Jain
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Patent number: 8738679Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.Type: GrantFiled: September 23, 2009Date of Patent: May 27, 2014Assignee: STMicroelectronics International N.V.Inventors: Rakhel Kumar Parida, Ankur Bal, Anupam Jain
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Patent number: 8731214Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: GrantFiled: April 23, 2010Date of Patent: May 20, 2014Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida