Abstract: A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

Abstract: A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: An embodiment of the invention may include a method and structure for determining a failure in a guard ring of a chip. The method may include measuring a current frequency of oscillation of a crack check circuit located within a guard ring. The method may include comparing the frequency to a baseline frequency of oscillation of the crack check circuit. The current frequency and baseline frequency may be normalized using a set of bypass lines. The method may include determining there is a failure of the guard ring based on the difference between the normalized frequency of oscillation and the baseline normalized frequency of oscillation.

Abstract: An electronic device includes a communication port, a display, a processor, and a memory. The processor detects whether an external device plugs into the communication port, displays a user interface on the display when an external device plugs into the communication port, detects whether the user interface receives a predetermined user operation, recommends relevant data linked to the external device according to predetermined rules when the user interface receives the predetermined user operation, and displays the relevant data linked to the external device on the display.

Abstract: An electronic device includes a display, a global positioning unit, a processor, and a memory. The global positioning unit establishes a location of the electronic device. The processor displays a user interface on the display, detects whether the user interface receives a predetermined gesture applied thereon, obtains a name of the location where the electronic device is located and a type of location corresponding to the name of the location when the predetermined gesture applied on the user interface is detected, and recommends relevant data on the user interface according to the type of location or the name of the location.

Abstract: A method for making a CMOS image sensor may include forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity types by forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, forming a first well around a periphery of the retrograde well also having the second conductivity type, and forming a second well within the retrograde well having the first conductivity type. Furthermore, first and second superlattices may be respectively formed overlying each of the first and second wells, with each of the first and second superlattices comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A differential charge pump circuit for use in a phase-locked loop (PLL) circuit is disclosed. The circuit includes a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The circuit controls a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node.

Abstract: Techniques for detailed monitoring and evaluation of individual subsystems within solar photovoltaic power generation systems are provided. In one aspect, a method for monitoring a photovoltaic system having at least one array of photovoltaic panels and at least one inverter system configured to convert output from the panels from DC to AC includes the steps of: obtaining sensor data from the photovoltaic system; computing an efficiency of the panels and an efficiency of the inverter system using the sensor data; computing an aging parameter for the panels using the efficiency of the panels; computing an aging parameter for the inverter system using the efficiency of the inverter system; determining whether the aging parameter for the panels or for the inverter system exceeds a predetermined threshold level; and taking action if either the aging parameter for the array or for the inverter system exceeds the predetermined threshold level.

Abstract: A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: There is provided a process for producing hydrocarbons from a reservoir. The process includes within the hydrocarbon reservoir, electrically heating a liquid heating fluid such that the liquid heating fluid is evaporated to produce a gaseous heating fluid, heating hydrocarbon material with the gaseous heating fluid such that the heated hydrocarbon material is mobilized and such that the gaseous heating fluid is condensed to produce a condensed heating fluid, and electrically heating at least a fraction of the condensed heating fluid such that the at least a condensed heating fluid fraction is re-evaporated, and while the evaporation, the condensing, and the re-evaporation are being effected, producing a produced fluid including at least the mobilized hydrocarbon material.

Abstract: A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: A system and apparatus relating to a differential charge pump circuit for use in a phase-locked loop (PLL) circuit. A differential charge pump circuit can include a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The nodes are inputs to one of the sense amplifiers. The differential charge pump circuit is configured to control a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node. The differential charge pump circuit can also include a transistor with a gate coupled to an output of a sense amplifier.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: There is provided a process for producing hydrocarbons from a reservoir. The process includes within the hydrocarbon reservoir, electrically heating a liquid heating fluid such that the liquid heating fluid is evaporated to produce a gaseous heating fluid, heating hydrocarbon material with the gaseous heating fluid such that the heated hydrocarbon material is mobilized and such that the gaseous heating fluid is condensed to produce a condensed heating fluid, and electrically heating at least a fraction of the condensed heating fluid such that the at least a condensed heating fluid fraction is re-evaporated, and while the evaporation, the condensing, and the re-evaporation are being effected, producing a produced fluid including at least the mobilized hydrocarbon material.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.