Patents by Inventor Ann Margaret Concannon
Ann Margaret Concannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527530Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.Type: GrantFiled: May 16, 2021Date of Patent: December 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishna Praveen Mysore Rajagopal, James Paul DiSarro, Ann Margaret Concannon, Rajkumar Sankaralingam
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Publication number: 20220223581Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.Type: ApplicationFiled: May 16, 2021Publication date: July 14, 2022Inventors: Krishna Praveen Mysore Rajagopal, James Paul DiSarro, Ann Margaret Concannon, Rajkumar Sankaralingam
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Patent number: 11271392Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.Type: GrantFiled: September 3, 2019Date of Patent: March 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ann Margaret Concannon, Vishwanath Joshi, Antonio Gallerano, Zhao Gao, Yanqing Li
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Patent number: 11239229Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: GrantFiled: November 26, 2018Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Patent number: 10763251Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.Type: GrantFiled: September 26, 2017Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishna Praveen Mysore Rajagopal, James P Di Sarro, Mariano Dissegna, Lihui Wang, Ann Margaret Concannon
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Patent number: 10749336Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.Type: GrantFiled: November 28, 2016Date of Patent: August 18, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
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Publication number: 20200235571Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.Type: ApplicationFiled: September 3, 2019Publication date: July 23, 2020Inventors: Ann Margaret Concannon, Vishwanath Joshi, Antonio Gallerano, Zhao Gao, Yanqing Li
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Publication number: 20190109127Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Publication number: 20190096874Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Applicant: Texas Instruments IncorporatedInventors: Krishna Praveen Mysore Rajagopal, James P. Di Sarro, Mariano Dissegna, Lihui Wang, Ann Margaret Concannon
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Patent number: 10163888Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: GrantFiled: November 23, 2016Date of Patent: December 25, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Publication number: 20180152019Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Applicant: Texas Instruments IncorporatedInventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
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Publication number: 20180145064Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Applicant: Texas Instruments IncorporatedInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Patent number: 9633990Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.Type: GrantFiled: June 21, 2016Date of Patent: April 25, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
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Patent number: 9633991Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.Type: GrantFiled: November 23, 2015Date of Patent: April 25, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
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Publication number: 20160300831Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.Type: ApplicationFiled: June 21, 2016Publication date: October 13, 2016Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
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Patent number: 9397085Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.Type: GrantFiled: December 22, 2014Date of Patent: July 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
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Publication number: 20160086936Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.Type: ApplicationFiled: November 23, 2015Publication date: March 24, 2016Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
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Patent number: 9224724Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.Type: GrantFiled: May 24, 2013Date of Patent: December 29, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
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Publication number: 20150187752Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.Type: ApplicationFiled: December 22, 2014Publication date: July 2, 2015Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
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Publication number: 20130320396Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.Type: ApplicationFiled: May 24, 2013Publication date: December 5, 2013Applicant: Texas Instruments IncorporatedInventors: Akram A. SALMAN, Farzan FARBIZ, Ann Margaret CONCANNON, Gianluca BOSELLI