Patents by Inventor Ann Margaret Concannon

Ann Margaret Concannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10763251
    Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, James P Di Sarro, Mariano Dissegna, Lihui Wang, Ann Margaret Concannon
  • Patent number: 10749336
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
  • Publication number: 20200235571
    Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.
    Type: Application
    Filed: September 3, 2019
    Publication date: July 23, 2020
    Inventors: Ann Margaret Concannon, Vishwanath Joshi, Antonio Gallerano, Zhao Gao, Yanqing Li
  • Publication number: 20190109127
    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 11, 2019
    Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
  • Publication number: 20190096874
    Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Krishna Praveen Mysore Rajagopal, James P. Di Sarro, Mariano Dissegna, Lihui Wang, Ann Margaret Concannon
  • Patent number: 10163888
    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
  • Publication number: 20180152019
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
  • Publication number: 20180145064
    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
  • Patent number: 9633990
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Patent number: 9633991
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Publication number: 20160300831
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 13, 2016
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Patent number: 9397085
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Publication number: 20160086936
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 24, 2016
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Patent number: 9224724
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Publication number: 20150187752
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Publication number: 20130320396
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 5, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Akram A. SALMAN, Farzan FARBIZ, Ann Margaret CONCANNON, Gianluca BOSELLI
  • Publication number: 20100190316
    Abstract: A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune.
    Type: Application
    Filed: April 2, 2010
    Publication date: July 29, 2010
    Applicant: National Semiconductor Corporation
    Inventors: Denis Finbarr O'Connell, Ann Margaret Concannon
  • Patent number: 7741190
    Abstract: A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: June 22, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Denis Finbarr O'Connell, Ann Margaret Concannon
  • Publication number: 20090042357
    Abstract: A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: Denis Finbarr O'Connell, Ann Margaret Concannon