Patents by Inventor Anna George

Anna George has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111745
    Abstract: A method includes performing a search of an inverted index structure indexing values of a column to generate an in-range indexed value set by identifying all indexed values of the inverted index structure falling within a range corresponding to a range-based filter. A set of characteristics of the in-range indexed value set are identified based on performing the search of an inverted index structure. When the set of characteristics compare favorably to the set of index-usage requirements, output is generated based on performing a plurality of searches to the inverted index structure based on the in-range indexed value set. When the set of characteristics compare unfavorably to the set of index-usage requirements, the output is generated without performing any searches to the inverted index structure.
    Type: Application
    Filed: September 15, 2023
    Publication date: April 4, 2024
    Applicant: Ocient Holdings LLC
    Inventors: Richard George Wendel, III, Greg R. Dhuse, Hassan Farahani, Matthew Ashbeck, Anna Veselova, Benjamin Daniel Rabe
  • Publication number: 20240095237
    Abstract: Identification of content gaps based on relative user-selection rates between multiple discrete content sources. A system analyzes search log activity to determine whether users that are conducting particular types of search activities are ultimately selecting and relying upon content resources from a predefined content source of interest or, alternatively, whether such users are unsatisfied with the predefined content source of interest and are instead relying upon other third-party content sources. This particular type of analysis provides valuable insights into whether content gaps exist within the predefined content source of interest.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Junia Anna GEORGE, Chetan BANSAL, Nikitha RAO, Casey Jo GOSSARD, Dung NGUYEN, David Boyd LUDWIG, IV, Curtis Dean ANDERSON
  • Patent number: 11868341
    Abstract: Identification of content gaps based on relative user-selection rates between multiple discrete content sources. A system analyzes search log activity to determine whether users that are conducting particular types of search activities are ultimately selecting and relying upon content resources from a predefined content source of interest or, alternatively, whether such users are unsatisfied with the predefined content source of interest and are instead relying upon other third-party content sources. This particular type of analysis provides valuable insights into whether content gaps exist within the predefined content source of interest.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 9, 2024
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Junia Anna George, Chetan Bansal, Nikitha Rao, Casey Jo Gossard, Dung Nguyen, David Boyd Ludwig, IV, Curtis Dean Anderson
  • Publication number: 20220121660
    Abstract: Identification of content gaps based on relative user-selection rates between multiple discrete content sources. A system analyzes search log activity to determine whether users that are conducting particular types of search activities are ultimately selecting and relying upon content resources from a predefined content source of interest or, alternatively, whether such users are unsatisfied with the predefined content source of interest and are instead relying upon other third-party content sources. This particular type of analysis provides valuable insights into whether content gaps exist within the predefined content source of interest.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 21, 2022
    Inventors: Junia Anna GEORGE, Chetan BANSAL, Nikitha RAO, Casey Jo GOSSARD, Dung NGUYEN, David Boyd LUDWIG, IV, Curtis Dean ANDERSON
  • Patent number: 7888183
    Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Cheng-Yi Liu, Johanna Swan, Steven Towle, Anna George, legal representative, Chuan Hu
  • Patent number: 7420273
    Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: September 2, 2008
    Assignee: Intel Corporation
    Inventors: Cheng-Yi Liu, Johanna Swan, Anna George, legal representative, Chuan Hu, Steven Towle
  • Publication number: 20080153209
    Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.
    Type: Application
    Filed: March 5, 2008
    Publication date: June 26, 2008
    Inventors: Cheng-Yi Liu, Johanna Swan, Steven Towle, Anna George, Chuan Hu
  • Publication number: 20070190776
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
    Type: Application
    Filed: April 25, 2007
    Publication date: August 16, 2007
    Applicant: Intel Corporation
    Inventors: Sarah Kim, Kevin Lee, Steven Towle, Anna George
  • Patent number: 7236666
    Abstract: Optical apparatus, methods of forming the apparatus, and methods of using the apparatus are disclosed herein. In one aspect, an optical apparatus may include a substrate, an on-substrate microlens coupled with the substrate to receive light from an off-substrate light emitter and focus the light toward a focal point, and an on-substrate optical device coupled with the substrate proximate the focal point to receive the focused light. Communication of light in the reverse direction is also disclosed. Systems including the optical apparatus are also disclosed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Anna George, legal representative, Henning Braunisch, Daoqiang Lu, Gilroy J. Vandentop, Steven Towle, deceased
  • Patent number: 7085449
    Abstract: A system is disclosed. The system includes an external waveguide and an IC coupled to the external waveguide. The IC includes at least two lenses and a second waveguide. The lenses couple radiant energy from the external waveguide to the second waveguide.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 1, 2006
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Anna George, legal representative, Daoqiang Lu, Gilroy Vandentop, Steven Towle, deceased
  • Publication number: 20060076678
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: November 16, 2005
    Publication date: April 13, 2006
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George
  • Publication number: 20060068518
    Abstract: Vertically aligned liquid crystal molecules may be formed using spin-on-glass deposition. After deposition, the molecules may be exposed to an oblique ion beam or e-beam bombardment. Other techniques for alignment involve microstructure formation such as using a double sided scrubber or high oxygen plasma processing. As a result, more conventional integrated circuit fabrication techniques may be utilized to form the vertically aligned liquid crystal layer giving higher reliability and a wider process window.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventor: Anna George
  • Publication number: 20060067606
    Abstract: Optical apparatus, methods of forming the apparatus, and methods of using the apparatus are disclosed herein. In one aspect, an optical apparatus may include a substrate, an on-substrate microlens coupled with the substrate to receive light from an off-substrate light emitter and focus the light toward a focal point, and an on-substrate optical device coupled with the substrate proximate the focal point to receive the focused light. Communication of light in the reverse direction is also disclosed. Systems including the optical apparatus are also disclosed.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Steven Towle, Henning Braunisch, Daoqiang Lu, Gilroy Vandentop, Anna George
  • Publication number: 20060051021
    Abstract: A system is disclosed. The system includes an external waveguide and an IC coupled to the external waveguide. The IC includes at least two lenses and a second waveguide. The lenses couple radiant energy from the external waveguide to the second waveguide.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 9, 2006
    Inventors: Henning Braunisch, Steven Towle, Daoqiang Lu, Gilroy Vandentop, Anna George
  • Publication number: 20060012039
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 19, 2006
    Inventors: Sarah Kim, Kevin Lee, Steven Towle, Anna George
  • Publication number: 20050266675
    Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.
    Type: Application
    Filed: July 6, 2005
    Publication date: December 1, 2005
    Inventors: Henning Braunisch, Steven Towle, Anna George
  • Publication number: 20050221598
    Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Daoqiang Lu, Steven Towle, Anna George
  • Publication number: 20050161789
    Abstract: An apparatus comprising a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, a die including an optical area, the die being flip-chip bonded to the substrate, and an optical inter-connector optically coupled to the optical area and at least partially positioned between the die and the base substrate, the optical inter-connector positioned in a trench formed in the solder resist layer and the conductive layer. A process comprising providing a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, forming a trench in the conductive layer and the solder resist layer, positioning a waveguide in the trench, and flip-chip bonding a die to the substrate, the die including an optical area, such that the optical area is optically coupled to the waveguide.
    Type: Application
    Filed: June 30, 2004
    Publication date: July 28, 2005
    Inventors: Steven Towle, Anna George
  • Publication number: 20050136640
    Abstract: A thinned die is disposed on a heat sink and bonded by a thermal interface material (TIM) that includes a gold-tin solder. The thinned die exhibits a die-effective coefficient of thermal expansion (CTE) that substantially matches the CTE of the heat sink. A process of bonding the die includes thermal bonding. A process of bonding the thinned die to a heat sink before bonding the die to an electrical interposer. A computing system includes a semconductive die that is gold-tin bonded to the heat sink, and it is coupled to at least one input-output device.
    Type: Application
    Filed: September 30, 2004
    Publication date: June 23, 2005
    Inventors: Chuan Hu, Steven Towle, Anna George
  • Publication number: 20050127528
    Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.
    Type: Application
    Filed: January 14, 2005
    Publication date: June 16, 2005
    Inventors: Daoqiang Lu, Steven Towle, Anna George