Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

Abstract: A method includes generating a sequence of images of a semiconductor wafer from first and second detectors. The first detector images the wafer with first imaging parameters and the second detector images the wafer with second imaging parameters. The first or second imaging parameters are varied across the sequence of images to provide variation at sites across the wafer. The method includes providing a metric indicative of center-of-symmetry variations of first and second target features as a function of the varied imaging parameters based on the sequence of images. The method includes identifying a landscape of values of the varied image parameters for which the metric are below a predefined limit. The method includes generating a recipe for metrology measurements in which the varied imaging parameters are set to values within the landscape. The method includes generating metrology measurements from a production wafer based on the recipe.

Abstract: A multiple-tool parameter set calibration and misregistration measurement method useful in the manufacture of semiconductor devices including using at least a first reference misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers on a wafer of a batch of wafers, thereby generating a first misregistration data set, transmitting the first set of parameters and the data set to a calibrated set of measurement parameters generator (CSMPG) which processes the first set of parameters and the data set thereby generating a calibrated set of measurement parameters which are transmitted from the CSMPG to calibrate at least one initially-uncalibrated misregistration metrology tool based on the calibrated set of measurement parameters.

Abstract: A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.

Abstract: A metrology target includes a first set of pattern elements compatible with a first metrology mode along one or more directions, and a second set of pattern elements compatible with a second metrology mode along one or more directions, wherein the second set of pattern elements includes a first portion of the first set of pattern elements, and wherein the second set of pattern elements is surrounded by a second portion of the first set of pattern elements not included in the second set of pattern elements.

Abstract: A system for analyzing one or more samples includes a sample analysis sub-system configured to perform one or more measurements on the one or more samples. The system further includes a controller configured to: receive design of experiment (DoE) data for performing the one or more measurements on the one or more samples; determine rankings for a set of target parameters; generate a recipe for performing the one or more measurements on the one or more samples based on the DoE data and the rankings of the set of target parameters; determine run parameters based on the recipe; perform the one or more measurements on the one or more samples, via the sample analysis sub-system, according to the recipe; and adjust the run parameters based on output data associated with performing the one or more measurements on the one or more samples.

Abstract: A product includes at least one semiconductor substrate, multiple thin-film layers disposed on the at least one substrate, and an overlay target formed in at least one of the thin-film layers. The overlay target includes a first sub-target having a first center of symmetry and including first target features having a first linewidth, and a second sub-target having a second center of symmetry coincident with the first center of symmetry and including second target features, which have a second linewidth, greater than the first linewidth, and are adjacent to but non-overlapping with the first target features.

Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

Abstract: Systems and methods of optimizing wafer transport and metrology measurements in a fab are provided. Methods comprise deriving and updating dynamic sampling plans that provide wafer-specific measurement sites and conditions, deriving optimized wafer measurement paths for metrology measurements of the wafers that correspond to the dynamic sampling plan, managing FOUP (Front Opening Unified Pod) transport through the fab, transporting wafers to measurement tools while providing the dynamic sampling plans and the wafer measurement paths to the respective measurement tools before or as the FOUPs with the respective wafers are transported thereto, and carrying out metrology and/or inspection measurements of the respective wafers by the respective measurement tools according to the derived wafer measurement paths.

Abstract: A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.

Abstract: A dynamic misregistration measurement amelioration method including taking at least one misregistration measurement at multiple sites on a first semiconductor device wafer, which is selected from a batch of semiconductor device wafers intended to be identical, analyzing each of the misregistration measurements, using data from the analysis of each of the misregistration measurements to determine ameliorated misregistration measurement parameters at each one of the multiple sites, thereafter ameliorating misregistration metrology tool setup for ameliorated misregistration measurement at the each one of the multiple sites, thereby generating an ameliorated misregistration metrology tool setup and thereafter measuring misregistration at multiple sites on a second semiconductor device wafer, which is selected from the batch of semiconductor device wafers intended to be identical, using the ameliorated misregistration metrology tool setup.

Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

Abstract: A product includes at least one semiconductor substrate, multiple thin-film layers disposed on the at least one substrate, and an overlay target formed in at least one of the thin-film layers. The overlay target includes a first sub-target having a first center of symmetry and including first target features having a first linewidth, and a second sub-target having a second center of symmetry coincident with the first center of symmetry and including second target features, which have a second linewidth, greater than the first linewidth, and are adjacent to but non-overlapping with the first target features.

Abstract: A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.

Abstract: A system for use with a misregistration metrology tool (MMT), the system including a database including a plurality of process variation (PV) categories and a corresponding plurality of parameter sets and a process variation accommodation engine (PVAE) including a measurement site process variation category associator (MSPVCA) operative to associate a measurement site being measured by the MMT, at least partially based on an MMT output relating to the measurement site, with a measurement site process variation category (MSPVC), the MSPVC being one of the plurality of PV categories, a measurement site parameter set retriever (MSPSR) operative to retrieve a measurement site parameter set (MSPS) corresponding to the MSPVC and a measurement site parameter set communicator (MSPSC) operative to communicate the MSPS to the MMT.

Abstract: A metrology system includes a controller communicatively coupled to one or more metrology tools, the controller including one or more processors configured to execute program instructions causing the one or more processors to receive one or more metrology measurements of one or more metrology targets of a metrology sample, a metrology target of the one or more metrology targets including one or more target designs with one or more cells, the one or more target designs being generated on one or more layers of the metrology sample; determine one or more errors based on the one or more metrology measurements; and determine one or more correctables to adjust one or more sources of error corresponding to the one or more errors, the one or more correctables being configured to reduce an amount of noise in the one or more metrology measurements generated by the one or more sources of errors.

Abstract: A data-driven misregistration parameter configuration and measurement system and method including simulating a plurality of measurement simulations of at least one multilayered semiconductor device, selected from a batch of multilayered semiconductor devices intended to be identical, using sets of measurement parameter configurations, generating simulation data for the device, identifying recommended measurement parameter configurations selected from sets of measurement parameter configurations, providing a multilayered semiconductor device selected from the batch, providing the at least one recommended set of measurement parameter configurations to a misregistration metrology tool having multiple possible sets of measurement parameter configurations, measuring at least one multilayered semiconductor device, selected from the batch, using the recommended set, thereby generating measurement data for the device, thereafter identifying a final recommended set of measurement parameter configurations and measuring

Abstract: A metrology system includes a controller communicatively coupled to one or more metrology tools, the controller including one or more processors configured to execute program instructions causing the one or more processors to receive one or more metrology measurements of one or more metrology targets of a metrology sample, a metrology target of the one or more metrology targets including one or more target designs with one or more cells, the one or more target designs being generated on one or more layers of the metrology sample; determine one or more errors based on the one or more metrology measurements; and determine one or more correctables to adjust one or more sources of error corresponding to the one or more errors, the one or more correctables being configured to reduce an amount of noise in the one or more metrology measurements generated by the one or more sources of errors.

Abstract: A multiple-tool parameter set calibration and misregistration measurement method useful in the manufacture of semiconductor devices including using at least a first reference misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers on a wafer of a batch of wafers, thereby generating a first misregistration data set, transmitting the first set of parameters and the data set to a calibrated set of measurement parameters generator (CSMPG) which processes the first set of parameters and the data set thereby generating a calibrated set of measurement parameters which are transmitted from the CSMPG to calibrate at least one initially-uncalibrated misregistration metrology tool based on the calibrated set of measurement parameters.

Abstract: Systems and methods of optimizing wafer transport and metrology measurements in a fab are provided. Methods comprise deriving and updating dynamic sampling plans that provide wafer-specific measurement sites and conditions, deriving optimized wafer measurement paths for metrology measurements of the wafers that correspond to the dynamic sampling plan, managing FOUP (Front Opening Unified Pod) transport through the fab, transporting wafers to measurement tools while providing the dynamic sampling plans and the wafer measurement paths to the respective measurement tools before or as the FOUPs with the respective wafers are transported thereto, and carrying out metrology and/or inspection measurements of the respective wafers by the respective measurement tools according to the derived wafer measurement paths.