Patents by Inventor Anna M. Prakash

Anna M. Prakash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9953929
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20170287851
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Application
    Filed: May 26, 2017
    Publication date: October 5, 2017
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li
  • Publication number: 20170271270
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20170266948
    Abstract: Described is an apparatus which comprises: a squeegee head which is operable to drop a material; and a vacuum manifold attachable to the squeegee head, wherein the vacuum manifold is operable to create a vacuum in a space prior to the squeegee head is to drop the material.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 21, 2017
    Inventors: Joshua D. Heppner, Shawna M. Liff, Eric J. Li, Anna M. Prakash
  • Publication number: 20170250145
    Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Rajendra C. Dias, Joshua D. Heppner, Mitul B. Modi, Anna M. Prakash
  • Publication number: 20170207152
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9704811
    Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Joshua D Heppner, Mitul B Modi, Anna M. Prakash
  • Publication number: 20170179040
    Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Rajendra C. Dias, Joshua D. Heppner, Mitul B. Modi, Anna M. Prakash
  • Publication number: 20170176495
    Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Wen Yin, Anna M. Prakash, Teag R. Haughan, Dingying David Xu, Joaquin Aguilar-Santillan
  • Patent number: 9685413
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li
  • Patent number: 9631065
    Abstract: Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Anna M. Prakash, James C. Matayabas, Arjun Krishnan, Nisha Ananthakrishnan
  • Patent number: 9613933
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20150255415
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, JR., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20140264827
    Abstract: Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Anna M. Prakash, James C. Matayabas, Arjun Krishnan, Nisha Ananthakrishnan
  • Patent number: 8183697
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy Ashton, II
  • Publication number: 20110074023
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 31, 2011
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy L. Ashton
  • Patent number: 7843075
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy L. Ashton
  • Patent number: 7776657
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: August 17, 2010
    Assignee: Intel Corporation
    Inventors: Ashay A. Dani, Anna M. Prakash, Saikumar Jayaraman, Mitesh Patel, Vijay S. Wakharkar
  • Patent number: 7651020
    Abstract: Embodiments include materials which may be used during electronic device fabrication, including a flux material. The flux material comprises a solution including a plurality of micellar structures in a solvent, the micellar structures each including a plurality of amphiphilic block copolymer elements. The amphiphilic block copolymer elements each include at least one non-polar region and at least one polar region. A fluxing agent is contained within the micellar structures. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Linda A. Shekhawat, Anna M. Prakash
  • Publication number: 20090273914
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 5, 2009
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy L. Ashton