Patents by Inventor Anna Maria Conti
Anna Maria Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220059763Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: ApplicationFiled: September 21, 2021Publication date: February 24, 2022Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Patent number: 11195998Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.Type: GrantFiled: June 8, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
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Publication number: 20210328142Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.Type: ApplicationFiled: May 5, 2021Publication date: October 21, 2021Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
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Patent number: 11133463Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: GrantFiled: April 23, 2020Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Publication number: 20210273015Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.Type: ApplicationFiled: May 14, 2021Publication date: September 2, 2021Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
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Publication number: 20210272615Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Patent number: 11037613Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: GrantFiled: July 17, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Patent number: 11018300Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.Type: GrantFiled: October 28, 2019Date of Patent: May 25, 2021Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
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Patent number: 11011582Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.Type: GrantFiled: February 7, 2020Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
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Publication number: 20210119123Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.Type: ApplicationFiled: November 3, 2020Publication date: April 22, 2021Inventors: Andrea Redaelli, Anna Maria Conti, Agostino Pirovano
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Publication number: 20210066394Abstract: One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.Type: ApplicationFiled: March 16, 2018Publication date: March 4, 2021Inventors: ANNA MARIA CONTI, Cristina CASELLATO, ANDREA REDAELLI
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Patent number: 10923387Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.Type: GrantFiled: September 20, 2019Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Marcello Mariani, Anna Maria Conti, Sara Vigano
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Publication number: 20210043685Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Andrea Redaelli, Anna Maria Conti
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Publication number: 20210020218Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Patent number: 10847719Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.Type: GrantFiled: May 18, 2020Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Anna Maria Conti, Agostino Pirovano
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Publication number: 20200321522Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: ApplicationFiled: April 23, 2020Publication date: October 8, 2020Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Publication number: 20200303642Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
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Publication number: 20200303640Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.Type: ApplicationFiled: May 18, 2020Publication date: September 24, 2020Inventors: Andrea Redaelli, Anna Maria Conti, Agostino Pirovano
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Publication number: 20200286957Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Anna Maria Conti, Fabio Pellizzer, Agostino Pirovano, Kolya Yastrebenetsky
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Publication number: 20200203606Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell