Patents by Inventor Anna Maria Conti
Anna Maria Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10693065Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.Type: GrantFiled: February 9, 2018Date of Patent: June 23, 2020Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Anna Maria Conti, Agostino Pirovano
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Patent number: 10680175Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.Type: GrantFiled: December 21, 2018Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
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Publication number: 20200176512Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.Type: ApplicationFiled: February 7, 2020Publication date: June 4, 2020Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
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Patent number: 10672981Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: GrantFiled: December 6, 2019Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Patent number: 10629261Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.Type: GrantFiled: April 1, 2019Date of Patent: April 21, 2020Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Davide Fugazza, Johannes A. Kalb
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Publication number: 20200119273Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: ApplicationFiled: December 6, 2019Publication date: April 16, 2020Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Patent number: 10600844Abstract: A memory structure can include a memory cell, a via, a dielectric material separating the memory cell from the via, a metal ceramic composite material layer on the memory cell and the dielectric material, and a conductive layer on the metal ceramic composite material layer and the via. The conductive layer can be in direct contact with the top surface of the via.Type: GrantFiled: September 28, 2018Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Anna Maria Conti, Andrea Redaelli
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Patent number: 10593730Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.Type: GrantFiled: October 10, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
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Publication number: 20200075858Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.Type: ApplicationFiled: October 28, 2019Publication date: March 5, 2020Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
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Patent number: 10541364Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: GrantFiled: February 9, 2018Date of Patent: January 21, 2020Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Publication number: 20200013829Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Applicant: Micron Technology, Inc.Inventors: Anna Maria Conti, Agostino Pirovano, Andrea Redaelli
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Publication number: 20200013669Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Applicant: Micron Technology, Inc.Inventors: Marcello Mariani, Anna Maria Conti, Sara Vigano
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Patent number: 10510957Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.Type: GrantFiled: July 26, 2017Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli
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Patent number: 10461128Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.Type: GrantFiled: April 26, 2017Date of Patent: October 29, 2019Assignee: Micron Technology, Inc.Inventors: Anna Maria Conti, Agostino Pirovano, Andrea Redaelli
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Patent number: 10460981Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.Type: GrantFiled: November 7, 2018Date of Patent: October 29, 2019Assignee: Micron Technology, Inc.Inventors: Marcello Mariani, Anna Maria Conti, Sara Vigano
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Publication number: 20190295642Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.Type: ApplicationFiled: April 1, 2019Publication date: September 26, 2019Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Davide Fugazza, Johannes A. Kalb
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Publication number: 20190252605Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Andrea Redaelli, Anna Maria Conti, Agostino Pirovano
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Publication number: 20190252606Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Anna Maria Conti, Fabio Pellizzer
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Patent number: 10276235Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.Type: GrantFiled: May 15, 2018Date of Patent: April 30, 2019Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Fabio Pellizzer, Anna Maria Conti, Davide Fugazza, Johannes A. Kalb
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Publication number: 20190088534Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.Type: ApplicationFiled: November 7, 2018Publication date: March 21, 2019Applicant: Micron Technology, Inc.Inventors: Marcello Mariani, Anna Maria Conti, Sara Vigano