Abstract: The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.

Abstract: The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

Abstract: A ring oscillator includes an oscillation module, a first delay module, and a second delay module. The oscillation module is disposed in a first delay loop and a second delay loop and includes a first number of latches connected in series. The oscillation module has two input ends and two output ends, and the two input ends are respectively connected to a first node and a second node. The first delay module is disposed in the first delay loop and has an input end connected to a first output end of the oscillation module and an output end connected to the first node. The second delay module is disposed in the second delay loop and has an input end connected to a second output end of the oscillation module and an output end connected to the second node.

Abstract: A voltage detection circuit including a threshold setting module and a voltage conversion module, and a voltage detection method are provided. In the threshold setting module, a first input end is configured to receive a voltage to be detected, a second input end is configured to receive a threshold regulation signal, a power supply end is connected to a first voltage and is configured to set a voltage regulation range according to the threshold regulation signal, determine a first voltage regulation value in the voltage regulation range according to the voltage to be detected, and generate a control voltage according to the first voltage and the first voltage regulation value. The voltage conversion module is configured to output a first level when the control voltage is greater than a preset value and output a second level when the control voltage is less than or equal to the preset value.

Abstract: Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.

Abstract: Embodiments of this invention provide a voltage output test circuit, a voltage divider output circuit, and a memory. The voltage output test circuit includes: a first voltage divider unit, including a first terminal and a second terminal, where the first terminal of the first voltage divider unit is connected to a test power supply, and the second terminal of the first voltage divider unit is connected to an output terminal; a second voltage divider unit, including a first terminal and a second terminal, where the first terminal of the second voltage divider unit is connected to a ground, and the second terminal of the second voltage divider unit is electrically connected to the output terminal; and a third voltage divider unit, configured to adjust a resistance between the output terminal and the ground.

Abstract: A ring oscillator includes: an oscillation module, disposed in the first delay loop and the second delay loop and including a first number of latches connected in series, where the oscillation module has two input ends and two output ends, and the two input ends are respectively connected to the first node and the second node; a first delay module, disposed in the first delay loop, having an input end connected to a first output end of the oscillation module and an output end connected to the first node, and including a second number of latches connected in series, where the second number is even; and a second delay module, disposed in the second delay loop, having an input end connected to a second output end of the oscillation module and an output end connected to the second node, and including the second number of latches connected in series.

Abstract: Embodiment provides an anti-fuse memory. An inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

Abstract: An MEMS device includes a package (1), a bottom plate (2), and a first inertial component (3). The first inertial component (3) is located in packaging space (4) formed by the bottom plate (2) and the package (1). There is a first alignment part (21) on a surface that is of the bottom plate (2) and that faces the packaging space (4), and the first inertial component (3) has a first mounting part (31). A shape of the first mounting part (31) matches a shape of the first alignment part (21). The MEMS device is equipped with a mounting alignment reference, the first mounting part (31) is connected to the first alignment part (21), and the first inertial component is mounted on the bottom plate at a preset angle. In addition, a bottom part of the first inertial component is not directly connected to the bottom plate.

Abstract: The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the symmetric ring oscillators are different.

Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.

Abstract: The invention relates to a silicon-based micro-machined vibratory gyroscope with an I-shaped structure, which is a measuring instrument used for measuring the angular rate perpendicular to a base, and comprises a top monocrystalline silicon, a middle monocrystalline silicon, and a bottom monocrystalline silicon; the top monocrystalline silicon being arranged with signal input and output lines is the silicon micro gyroscope packaged cover plate; the middle monocrystalline silicon is where the gyroscope mechanical structures are fabricated; the bottom monocrystalline silicon is a gyroscope substrate with fixed pedestals; the middle monocrystalline silicon layer is sealed in a closed cavity formed by top and bottom monocrystalline silicon layers.

Abstract: The invention relates to a silicon-based micro-machined vibratory gyroscope with an I-shaped structure, which is a measuring instrument used for measuring the angular rate perpendicular to a base, and comprises a top monocrystalline silicon, a middle monocrystalline silicon, and a bottom monocrystalline silicon; the top monocrystalline silicon being arranged with signal input and output lines is the silicon micro gyroscope packaged cover plate; the middle monocrystalline silicon is where the gyroscope mechanical structures are fabricated; the bottom monocrystalline silicon is a gyroscope substrate with fixed pedestals; the middle monocrystalline silicon layer is sealed in a closed cavity formed by top and bottom monocrystalline silicon layers.