Abstract: A gapless ferrite structure for circulator or isolator includes a first base having a first flange and a first limit slot surrounded by the first flange, a second base having a second flange and a second limit slot surrounded by the second flange, a ferrite with two ends accommodated in the first limit slot and the second limit slot respectively, two limit magnets installed on the first base and the second base respectively and configured to be corresponsive to the ferrite to generate an attraction force on the ferrite, and two sealing units configured between an end of the ferrite and the first limit slot and between the other end of the ferrite and the second limit slot respectively. In this way, a gapless structure can be formed on a signal transmission path in a circulator or isolator.

Abstract: A cross-coupling structure for dielectric cavity filters includes a base and a tuner. The base is communicated with plural resonant cavities, a side through hole and a blind hole, and has a first channel formed between two adjacent resonant cavities which are not used for producing cross-coupling, and a second channel the resonant cavities formed between two adjacent resonant cavities which are used for producing cross-coupling. The side through hole is penetrated through the base and communicated with the second channel. The blind hole is formed on a wall of the second channel and has an opening facing the side through hole. The tuner is entered into the second channel from the side through hole and extended into the blind hole and can be adjustably moved between the opening of the blind hole and the bottom of the blind hole to set a cross-coupling amount target value.

Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: An aza-ergoline derivative and a preparation method therefor and an application thereof. The derivative has a structure as shown in formula (I). The aza-ergoline derivative has good affinity, agonistic activity or selectivity to a dopamine D2 receptor.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: The present disclosure relates to a thermoplastic pulverulent composition comprising (a) at least one silica particle treated with alkoxysilane; and (b) at least one thermoplastic polymer. The present disclosure also relates to a 3D-printed object formed from the thermoplastic pulverulent composition and a process of forming the 3D-printed object. The thermoplastic pulverulent composition shows good powder flowability and the printed object obtained from said thermoplastic pulverulent composition surprisingly shows high elongation at break, high impact strength, good toughness and low surface roughness.

Abstract: A variable aperture module includes a blade assembly including movable blades, a positioning element including positioning structures and a driving part including a rotation element. The movable blades are disposed around an optical axis to form a light passable hole with adjustable size for different hole size states and each have an inner surface to define the contour of the light passable hole in each hole size state. The positioning structures correspond to the movable blades. The rotation element is rotatable with respect to the positioning element and is configured to rotate the movable blades to adjust a size of the light passable hole. There are matte structures disposed on each inner surface. Each matte structure is single structure extending towards the optical axis, such that at least part of the contour of the light passable hole has an undulating shape at least in several hole size states.

Abstract: The present disclosure provides a wind turbine blade with an improved trailing edge structure and a manufacturing method thereof. The wind turbine blade includes an upper shell, a lower shell, and a trailing edge, where a trailing edge bonding region enclosed by the upper shell, the lower shell and the trailing edge is filled with composite materials, and the composite materials are discontinuous in an airfoil chordwise direction. The manufacturing method includes the following steps: S1: manufacturing reinforcements with a same cross-sectional shape as the trailing edge filling region for composite materials; and S2: integrally molding the reinforcements, a fiber fabric and the upper shell, providing the lower shell, combining the upper shell and the lower shell, and performing heating for curing and molding. The discontinuous filling structure reduces usages of the adhesive and the reinforcements of the composite materials.

Abstract: An image sensor and method for fabricating are provided. The image sensor includes: a semiconductor substrate with multiple pixel regions formed thereon; adhesive frame formed on the semiconductor substrate, the adhesive frame including a peripheral adhesive frame arranged along the periphery of the semiconductor substrate and multiple reaction well adhesive frames disposed within the peripheral adhesive frame; a biological liquid crystal filled at least in each of the reaction well adhesive frames, the biological liquid crystal having an antigen-modified or an antibody-modified liquid crystal sensing interface; a glass coverplate disposed opposite to the semiconductor substrate; and a bonding layer, bonding the adhesive frames to the glass coverplate and loses a bonding power when heated or irradiated by UV light.

Abstract: A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Abstract: An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.

Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.

Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

Abstract: An antenna structure includes a ground element, a feeding radiation element, a shorting radiation element, a connection radiation element, a first radiation element, and a second radiation element. The feeding radiation element has a feeding point. The feeding radiation element is coupled through the shorting radiation element to the ground element. The connection radiation element is coupled between the first radiation element and the shorting radiation element. The second radiation element is coupled to the feeding radiation element. A coupling slot region is formed and substantially surrounded by the feeding radiation element, the shorting radiation element, the connection radiation element, the first radiation element, and the second radiation element.

Abstract: A power distribution device includes a substrate, a first chip, a first bump, a second bump and a first capacitor. The first chip is configured to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first chip, and configured to transmit the first reference voltage signal from the substrate to the first chip. The second bump is located between the substrate and the first chip, and configured to transmit the second reference voltage signal from the substrate to the first chip. The first capacitor is located above the substrate and below the first chip. A first terminal of the first capacitor is coupled to the first bump, and a second terminal of the first capacitor is coupled to the second bump. A power distribution system is also disclosed herein.

Abstract: A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.