Abstract: An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.

Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

Abstract: This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

Abstract: This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Abstract: An extendable imager configured to capture an image responsive to a command from a mobile device and an arm coupled to the imager, the arm configured to extend the imager from a surface of the mobile device.

Abstract: This disclosure describes systems, methods, and computer-readable media related to wireless displays with audio skipping. In some embodiments, a plurality of audio packets may be captured. Each of the plurality of audio packets may be analyzed. Analyzing the packets may include determining whether an audio packet of the plurality of audio packets is silent. In response to determining the audio packet of the plurality of audio packets is not silent, an audio non-skip mode may be entered. In response to determining the audio packet of the plurality of audio packets is silent, a determination may be made as to whether an indicator has exceeded a threshold. The indicator may indicate a sequential number of silent audio packets. In response to the indicator indicating the indicator exceeds the threshold, an audio skip mode may be entered. In response to the indicator indicating the indicator has not exceeded the threshold, the audio non-skip mode may be entered.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Abstract: An electronic device is provided that includes an input device to provide first audio signals, an output device to receive second audio signals, and logic to receive the first audio signals and to provide an audio input flow. The logic to further receive an audio output flow and to provide the second audio signals to the output device based on the audio output flow. The audio device to further align the audio input flow relative to the audio output flow.

Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

Abstract: A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.

Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

Abstract: This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

Abstract: Provided are techniques for processing a data segment by stripping a header from a transport layer segment, performing protocol data unit detection to determine data for a protocol segment that is part of the transport layer segment data, and performing marker validation and stripping.

Abstract: A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.