Abstract: A method and circuit for optimizing power consumption and performance of driver circuits are described. More particularly, embodiments of the present invention provide an enhanced driver circuit. The enhanced driver circuit provides a first voltage, and a detector coupled to the enhanced driver that monitors the first voltage. If the first voltage falls below a predetermined value, the enhanced driver increases the first voltage to at least an optimal voltage.

Abstract: A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

Abstract: A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit. A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges.

Abstract: An incoming signal's duty cycle is transformed to a known value by a first programmable duty cycle generator, and the output of the first programmable duty cycle generator is applied to a second programmable duty cycle generator which includes multiple stages which provide multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other by voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

Abstract: A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle.

Abstract: A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged.

Abstract: A precise programmable duty cycle generator employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle. The present invention transforms an incoming signal's duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outputs, each having a different known value of a precise duty cycle.

Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: A precise and programmable duty cycle adjuster which can produce a user definable duty cycle clock signal comprises a digital to analog converter (DAC), low pass filter (LPF), operational transconductance amplifier (OTA), and a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit employs a number of delay stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. For a fixed number of delay stages, the range of duty cycle selection is inversely proportional to the frequency of an input clock signal. This frequency range limitation is alleviated by designing the VCDCG with a multiple number of delay taps in conjunction with multiple tap points which are multiplexed at the output.

Abstract: A system and method for accurately measuring the duty cycle of an input periodic pulsed signal. The system includes a device for converting the input signal to be measured into a first dc voltage and, a device maintaining representations of potential duty cycle values that are selectable in an iterative fashion. At each iteration, in response to a selected duty cycle value, a second dc voltage is generated that represents the difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value. A selection mechanism responds to the first and second dc voltages for selecting a different encoded duty cycle for a successive iteration. The system selects an encoded duty cycle value at each iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof.

Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: A system and method of controlling the operation of a storage device (a semiconductor latch in its preferred embodiment) to reduce the power consumed by the storage device. The system uses a split clock signal to control the operation of the latch, with an early enable signal and a late enable signal being operable to turn the latch on when needed and to turn it off when it is not needed. More particularly, the present invention logically generates clocking control signals for the latch using the early enable signal and the late enable signal to control the operation of the latch and to reduce power consumption and allow for an increased period of time to make a decision whether to turn off the early enable signal.

Abstract: The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to fuses and redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array.

Abstract: A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.

Abstract: A specific structure which improves the decoupling capacitance for the power conductors in parallel metal layers of a semiconductor device. The power conductors are arranged so that conductors vertically adjacent to each other in the two outer of three metal layers are never connected to the same supply voltage terminal, but rather to opposing terminals. To improve current carrying capacity and reduce area, a power conductor in one outer plane is connected to a power conductor in the other outer plane which is displaced vertically and laterally from the first power conductor. The connection is made through special stitch conductors in the intervening plane. The resulting structure improves power supply decoupling for the finished device by providing significantly greater capacitance associated with the power distribution system of the chip.

Abstract: A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.

Abstract: A VLSI chip is disclosed having reduced power dissipation. This is accomplished by limiting the output voltage swing at the output of off chip driver circuits by utilization of a control circuit to regulate the gate bias voltage of an NFET pull-up transistor coupled to the output of the driver circuit and by feeding back the output of the driver circuit to the control circuit.

Abstract: The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both.

Abstract: The present invention utilizes bypass circuitry to shorten the cycle time of a cache memory by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time.

Abstract: A voltage generator, for providing bias voltages which bias static CMOS circuits, includes at least one pull-up device coupled through an output circuit arrangement to a plurality of compensation circuits. The compensation circuits adjust the bias voltage to compensate for supply voltage tolerances and variations caused by device process dependent parameters.