Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack (101?, 102?, 103?) on a substrate (10?, 100?) which has a principal surface. The multilayer stack includes a supporting layer (102?) formed over the principal surface of the substrate and a photoresist layer (103?) formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material on a principal surface of a substrate, depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.

Abstract: A device includes: a substrate including a superconductor quantum device, the superconductor quantum device including a superconductor material that exhibits superconducting properties at or below a corresponding critical temperature; a cap layer bonded to the substrate; and a sealed cavity between the cap layer and the substrate.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: A computer-implemented method for simulating quantum hardware performance can include accessing, by a computing system including one or more computing devices, a quantum hardware sample generation model configured to generate quantum hardware samples. The quantum hardware sample generation model can include one or more quantum hardware parameters. The computer-implemented method can include sampling, by the computing system, a quantum hardware sample from the quantum hardware sample generation model. The computer-implemented method can include obtaining, by the computing system, one or more simulated performance measurements based at least in part on the quantum hardware sample.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material (100?) on a principal surface of a substrate (10), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer (104?) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: Methods, systems and apparatus for implementing a target two-qubit quantum logic gate on a first qubit and second qubit using a tunable qubit coupler. In one aspect, a method includes generating a control signal for the target two-qubit quantum logic gate according to a control model, wherein the control model comprises a controlled-Z operator and a swap operator that are non-orthogonal; and applying the control signal to the first qubit, second qubit and tunable qubit coupler.

Abstract: A device includes: a substrate including a superconductor quantum device, the superconductor quantum device including a superconductor material that exhibits superconducting properties at or below a corresponding critical temperature; a cap layer bonded to the substrate; and a sealed cavity between the cap layer and the substrate.

Abstract: Methods, systems and apparatus for implementing a tunable qubit coupler. In one aspect, a device includes: a first data qubit, a second data qubit, and a third qubit that is a tunable qubit coupler arranged to couple to the first data qubit and to couple to the second data qubit such that, during operation of the device, the tunable qubit coupler allows tunable coupling between the first data qubit and the second data qubit.

Abstract: Methods, systems and apparatus for implementing a target two-qubit quantum logic gate on a first qubit and second qubit using a tunable qubit coupler. In one aspect, a method includes generating a control signal for the target two-qubit quantum logic gate according to a control model, wherein the control model comprises a controlled-Z operator and a swap operator that are non-orthogonal; and applying the control signal to the first qubit, second qubit and tunable qubit coupler.

Abstract: A device includes: a substrate including a superconductor quantum device, the superconductor quantum device including a superconductor material that exhibits superconducting properties at or below a corresponding critical temperature; a cap layer bonded to the substrate; and a sealed cavity between the cap layer and the substrate.

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

Abstract: A device includes: a substrate including a superconductor quantum device, the superconductor quantum device including a superconductor material that exhibits superconducting properties at or below a corresponding critical temperature; a cap layer bonded to the substrate; and a sealed cavity between the cap layer and the substrate.

Abstract: Methods, systems and apparatus for implementing a tunable qubit coupler. In one aspect, a device includes: a first data qubit, a second data qubit, and a third qubit that is a tunable qubit coupler arranged to couple to the first data qubit and to couple to the second data qubit such that, during operation of the device, the tunable qubit coupler allows tunable coupling between the first data qubit and the second data qubit.

Abstract: A parametric traveling wave amplifier (200) is disclosed in which the amplifiers include: a co-planar waveguide, in which the co-planar waveguide includes at least one Josephson junction (210) interrupting a center trace (204) of the co-planar waveguide; and at least one shunt capacitor coupled to the co-planar waveguide, in which each shunt capacitor of the at least one shunt capacitor includes a corresponding superconductor trace (214) extending over an upper surface of the center trace of the co-planar waveguide, and in which a gap separates the superconductor trace from the upper surface of the center trace, and in which the co-planar waveguide including the at least one Josephson junction and the shunt capacitor establish a predefined overall impedance for the traveling wave parametric amplifier.

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

Abstract: A quantum computing device includes: a qubit; a single XYZ control line, in which the qubit and the single control line are configured and arranged such that, during operation of the quantum computing device, the single XYZ control line allows coupling of an XY qubit control flux bias, from the single XYZ control line to the qubit, over a first frequency range at a first predetermined effective coupling strength, and coupling of a Z qubit control flux bias, from the single XYZ control line to the qubit, over a second frequency range at a second predetermined effective coupling strength.