Abstract: A method is presented, including providing an offset magnetic flux bias to a plurality of superconducting qubits and providing respective control magnetic flux biases, for performing a computation, to the plurality of qubits using a plurality of control lines coupled respectively to each qubit. The qubits are configured such that respective resonance frequencies of the qubits are controlled by the offset magnetic flux bias and the respective control magnetic flux biases. The qubits are arranged to perform the computation when the respective resonance frequencies of the qubits are within an operational dynamic range.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: Methods, systems and apparatus for implementing two-qubit gates using a tunable coupler. In one aspect, a method of implementing a two-qubit gate includes: applying a unitary transformation control signal to a tunable coupler arranged between a first data qubit and a second data qubit to obtain a target unitary transformation of the first data qubit and the second data qubit, w'herein the unitary transformation control signal is applied to the tunable coupler over a predetermined period of time to allow coupling between the first data qubit and the second data qubit through the tunable coupler.

Abstract: A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow.

Abstract: A quantum device includes: a substrate; and at least three co-planar structures arranged on a surface of the substrate, each co-planar structure, of the at least three co-planar structures, including a superconductor, in which a first effective dielectric constant between a first co-planar structure and a second co-planar structure that is a nearest neighbor to the first co-planar structure is above a first threshold, a second effective dielectric constant between the first co-planar structure and a third co-planar structure that is a next nearest neighbor to the first so-planar structure is less than a second threshold, and the second threshold is less than the first threshold.

Abstract: Methods, systems and apparatus for implementing a tunable qubit coupler. In one aspect, a device includes: a first data qubit, a second data qubit, and a third qubit that is a tunable qubit coupler arranged to couple to the first data qubit and to couple to the second data qubit such that, during operation of the device, the tunable qubit coupler allows tunable coupling between the first data qubit and the second data qubit.

Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material (100?) on a principal surface of a substrate (10), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer (104?) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.

Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack (101?, 102?, 103?) on a substrate (10?, 100?) which has a principal surface. The multilayer stack includes a supporting layer (102?) formed over the principal surface of the substrate and a photoresist layer (103?) formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

Abstract: A quantum device includes: a substrate; and at least three co-planar structures arranged on a surface of the substrate, each co-planar structure, of the at least three co-planar structures, including a superconductor, in which a first effective dielectric constant between a first co-planar structure and a second co-planar structure that is a nearest neighbor to the first co-planar structure is above a first threshold, a second effective dielectric constant between the first co-planar structure and a third co-planar structure that is a next nearest neighbor to the first so-planar structure is less than a second threshold, and the second threshold is less than the first threshold.

Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.