Patents by Inventor Anthony Eugene Zortea
Anthony Eugene Zortea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742869Abstract: A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.Type: GrantFiled: January 11, 2022Date of Patent: August 29, 2023Assignee: Mellanox Technologies, Ltd.Inventors: Anthony Eugene Zortea, Hananel Faig, Boris Sharav, Mor Goren, Alik Gorshtein, Nir Sheffi
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Publication number: 20230223946Abstract: A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Inventors: Anthony Eugene Zortea, Hananel Faig, Boris Sharav, Mor Goren, Alik Gorshtein, Nir Sheffi
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Patent number: 10587281Abstract: A system and method for sampling an RF signal uses a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: GrantFiled: September 28, 2018Date of Patent: March 10, 2020Assignee: Maxlinear Asia Singapore PTE LTDInventors: William Michael Lye, Anthony Eugene Zortea, Jatinder Chana
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Publication number: 20190036539Abstract: A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Inventors: William Michael LYE, Anthony Eugene ZORTEA, Jatinder CHANA
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Patent number: 10141945Abstract: A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: GrantFiled: December 4, 2017Date of Patent: November 27, 2018Assignee: Maxlinear Asia Singapore PTE LTDInventors: William Michael Lye, Anthony Eugene Zortea, Jatinder Chana
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Publication number: 20180091166Abstract: A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: ApplicationFiled: December 4, 2017Publication date: March 29, 2018Inventors: William Michael LYE, Anthony Eugene ZORTEA, Jatinder CHANA
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Patent number: 9866228Abstract: A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.Type: GrantFiled: September 29, 2016Date of Patent: January 9, 2018Assignee: MULTIPHY LTD.Inventors: Anthony Eugene Zortea, Russell Romano
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Patent number: 9847788Abstract: A system for sampling an RF signal comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: GrantFiled: August 19, 2016Date of Patent: December 19, 2017Assignee: Maxlinear Asia Singapore PTE LTDInventors: William Michael Lye, Anthony Eugene Zortea, Jatinder Chana
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Patent number: 9749070Abstract: The peak level of a high frequency analog signal in an RF receiver is detected by a system which samples the signal and compares it against a static threshold, generating an above/below status. The system is implemented with a sampler of sufficient aperture bandwidth to capture the signal in question, operated at a clock frequency, dynamically chosen as a function of fLO (local oscillator frequency) and the desired fIF (intermediate frequency), to minimize in-band intermodulation products. The sampler produces kickback intermodulation products that are positioned out-of-band, or are of low enough power in-band so as to be inconsequential. Samples are taken for a statistically significant period of time, and the status is used to adapt the threshold to systematically determine the peak amplitude of the signal being observed.Type: GrantFiled: January 19, 2016Date of Patent: August 29, 2017Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.Inventors: Russell Romano, Anthony Eugene Zortea
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Patent number: 9692436Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.Type: GrantFiled: October 21, 2016Date of Patent: June 27, 2017Assignee: MULTIPHY LTD.Inventors: Anthony Eugene Zortea, Russell Romano
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Patent number: 9680489Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.Type: GrantFiled: September 29, 2016Date of Patent: June 13, 2017Assignee: MULTIPHY LTD.Inventors: Anthony Eugene Zortea, Russell Romano
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Patent number: 9680490Abstract: System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.Type: GrantFiled: August 17, 2016Date of Patent: June 13, 2017Assignee: MULTIPHY LTD.Inventors: Anthony Eugene Zortea, Russell Romano
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Publication number: 20170117915Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.Type: ApplicationFiled: October 21, 2016Publication date: April 27, 2017Applicant: MULTIPHY LTD.Inventors: Anthony Eugene ZORTEA, Russell ROMANO
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Publication number: 20170099061Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.Type: ApplicationFiled: September 29, 2016Publication date: April 6, 2017Applicant: MULTIPHY LTD.Inventors: Anthony Eugene ZORTEA, Russell ROMANO
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Publication number: 20170093415Abstract: A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.Type: ApplicationFiled: September 29, 2016Publication date: March 30, 2017Applicant: MULTIPHY LTD.Inventors: Anthony Eugene ZORTEA, Russell ROMANO
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Publication number: 20170054448Abstract: A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.Type: ApplicationFiled: August 19, 2016Publication date: February 23, 2017Inventors: William Michael LYE, Anthony Eugene ZORTEA, Jatinder CHANA
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Publication number: 20170054447Abstract: System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.Type: ApplicationFiled: August 17, 2016Publication date: February 23, 2017Applicant: MULTIPHY LTD.Inventors: Anthony Eugene ZORTEA, Russell ROMANO
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Publication number: 20170054510Abstract: An electro-optical FIR transmit filter comprising a segmented MZM including a plurality of MZM segments, for receiving an input optical traveling wave to be filtered; an electrical field driver, for applying a controlled electrical field required for modulation of each MZM using a control signal which controls the electrical field; delay cells associated with at least one MZM, for aligning the control signal with a travelling optical wave; and at least one electrical xT delay cell representing a filter delay, for electrically adjusting the timing of the control signal. The FIR filter's coefficients are implemented in the optical domain by determining the amount of MZM segments driven by each xT delay cell, with respect to the total number of MZM segments.Type: ApplicationFiled: August 16, 2016Publication date: February 23, 2017Applicant: MULTIPHY LTD.Inventors: Anthony Eugene ZORTEA, Dan SADOT, Russell ROMANO
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Patent number: 9350399Abstract: A method and apparatus are provided for reducing aliasing in a direct conversion (or zero-IF) radio receiver having high and low frequency paths. According to an implementation, a non-transitory machine-readable memory stores aliasing correlation response data that associates a measured non-aliased signal in a high frequency path and a measured aliased residual of the signal in a low frequency path. A compensator is in communication with the memory to apply aliasing compensation to received signals based on the stored aliasing correlation response data. In an example implementation, the low and high frequency paths are independently optimized for low and high frequency performance, respectively, and have transfer functions that overlap with one another to create a calibration zone used to calibrate the first and second transfer functions.Type: GrantFiled: December 19, 2014Date of Patent: May 24, 2016Assignee: Microsemi Storage Solutions (U.S.), Inc.Inventors: Anthony Eugene Zortea, Mark Hiebert
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Patent number: 9344272Abstract: Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a post-cursor. However, for example, when the impulse response of an associated transmission line is not symmetric, the main cursor can be misaligned by conventional Mueller-Muller techniques. By providing a replica clock and data recovery path, trial and error experiments on the phase detector offset and/or gain can be performed, and relatively good values found for the phase detector offset and/or gain without disturbing the reception of data by the phase detector that is being used to receive data. These settings can then be used by the phase detector that is being used to receive data, which can improve the bit error rate of the phase detector.Type: GrantFiled: January 26, 2015Date of Patent: May 17, 2016Assignee: Microsemi Storage Solutions, Inc.Inventors: Anthony Eugene Zortea, William D. Warner