Abstract: Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.

Abstract: An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.

Abstract: DC offsets in high-gain amplifiers should be corrected to avoid the signal distortion that would result from amplifier saturation. A predominantly digital technique is described in which a digital algorithm observes patterns in the sign of the amplifier output and drives a digital-to-analog converter (DAC), which reduces the amplifier's offset.

Abstract: There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system performance requirements allow. Relatively low power dissipation occurs when the histogram of logic path delays is packed towards the critical path delay, and the critical path delay is relatively close to the system clock period. In one embodiment, power is reduced by arranging path delays to be relatively slow. In one embodiment, the histogram of path delays is shaped by establishing classes of paths based on path delay, and individually controlling the classes to slow each class down, preferably relatively close to the delay of the critical path.

Abstract: Methods and apparatus for canceling pre-cursor inter-symbol interference (ISI) are disclosed. In a digital communication system, a significant amount of noise can be attributed to the pre-cursor portion of the ISI. In a receiver, it can be relatively difficult to compensate for pre-cursor ISI in part because pre-cursor ISI is a result of one or more symbols that have yet to arrive at the receiver. One embodiment removes a portion of this ISI by using multiple detection thresholds in parallel. For example, data slicing (generation of a hard decision) can include three thresholds. These thresholds for slicing include a positive offset, a negative offset and no offset. The positive and negative offsets can correspond to the expected pre-cursor component of the data channel for which the data is transmitted or to a fraction thereof. The path with the correctly-compensated ISI is selected later.

Abstract: An apparatus uses a “self-organizing” method to eliminate or at least partially compensate for undesired or unexpected threshold errors encountered in analog-to-digital conversions. The self-organizing feature results in a relatively good, such as an optimal, spacing of a plurality of comparator thresholds even in the presence of relatively large comparator offsets, reference offsets, or other system offsets. Advantageously, the self-organizing techniques can be used without a special starting point for the thresholds. The self-organizing techniques can be used applied to at least portions of any analog-to-digital converter ADC that uses comparators, such as flash ADCs, pipeline ADCs, and sub-ranging ADCs.

Abstract: A bi-directional communication link has plural channels with respective masters and slaves at respective ends of respective channels, in which each master issues a Master Tx clock, each slave constructs a Slave Rx clock frequency locked to the Master Tx clock, and a Slave Tx clock frequency locked to the Slave Rx clock. A metric processor for each master produces a metric signal indicative of resolution of a signal received by the master from the corresponding slave. A decision processor responsive to the metric processor changes the phase of the Slave Tx clock relative to the Slave Rx clock so as to maximize the metric signal. In one embodiment, the resolution is a resolution between leading and trailing edges of the received signal. In another embodiment, the resolution is a resolution between allowed amplitude levels of the received signal.

Abstract: A receiver has an equalizer with plural equalization settings, which compensates for distortion in a received signal, and an adapter for selecting one of those settings which optimally compensates for the distortion. The adapter employs a trial and error procedure for evaluating equalizer performance for each such setting by first observing multiple levels of the incoming signal and defining therefrom valid regions, encompassing each of the multiple levels, and invalid regions. For each setting, the adapter computes first and second metrics respectively consisting of a count of samples within each of the invalid regions, and differences that are less than a predetermined threshold between pairs of samples falling within that valid region. For each setting, the adapter combines the metrics to produce a combined metric. The adapter then compares all of the combined metrics to determine the best metric and chooses the setting corresponding thereto.

Abstract: The invention is embodied in an adapter for use with a near end crosstalk (NEXT) canceller which reduces crosstalk, from a locally transmitted signal, in a locally received digital signal by superimposing, on the received signal, a correction signal comprising a sum of m largest time-delayed weighted and bandpass filtered samples of the transmitted signal spanning a range of n time delayed values, where m<n.

Abstract: The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a recovered clock to produce a succession of samples of the analog signal. The low sampling rate may be within an order of magnitude of the symbol rate of the analog signal. Each sample is converted to a digital word. A phase detector reference circuit determines from peak values of the analog signal at least two allowable levels of the analog signal including a reference-crossing level. The phase detector defines a zero band of amplitude ranges of the analog signal including the reference-crossing level. It further defines an error band of amplitude ranges of the analog signal extending from said zero band to a fraction of the amplitude of the next allowable level. The phase detector then infers either a positive or negative phase error for each pair of successive samples of the analog signal.

Abstract: The invention is embodied in an adaptive filtering system for processing a received signal, including a signal processor having plural states to generate a processed signal from the received signal in accordance with a selected one of the states. A slicer produces from the processed signal a pulse signal as an output signal of said adaptive filtering system. A eye-diagram calculator produces from the pulse signal a metric signal corresponding to a minimal separation between leading and trailing edges of a succession of n pulses in the pulse signal superimposed upon one another within a repetitive sampling window. An adaptive controller responsive to the metric signal finds the one state of the signal processor that optimizes the metric signal, and places the signal processor into that state.

Abstract: In a high speed digital communication receiver, an n-stage oscillator of frequency f has a plurality of n stages with n variable analog delays connected to respective ones of the n stages, outputs of the n variable analog delays providing n successive cycles of a clock signal of frequency n×f. A delay control circuit varies the delay interposed by each of the variable delays through a range of 1/(n×f). The delay control circuit can vary the delay in m equal steps, whereby the oscillator exhibits n×m virtual oscillator stages, so that the oscillator provides a phase resolution of 1/(m×n×f).

Abstract: A method is provided for testing a communication circuit. Power is applied to a clock recovery circuit. A precharge bit is provided to the clock recovery circuit after applying power to the clock recovery circuit. A predetermined number of pulses is provided to a charge pump coupled to a voltage controlled oscillator to initialize the voltage controlled oscillator to near an operating frequency.

Abstract: A method in a communication circuit recovers a clock signal. A voltage controlled oscillator is initialized by supplying a predetermined.number of pulses to a charge pump coupled to the voltage controlled oscillator so as to initialize the voltage controlled oscillator to near an operating frequency upon power up of . the clock recovery circuit.

Abstract: In at least one implementation, a method is provided for testing a communication circuit having a clock recovery circuit. The method comprising initializing a voltage controlled oscillator to near an expected operating frequency upon power up of the clock recovery circuit by supplying a signal from an external tester.