Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Abstract: According to at least one example, an amplifier circuit includes an amplifier and a temperature sensor circuit. The temperature sensor circuit includes a first transistor thermally isolated from the amplifier and being configured to sense an ambient temperature, and a second transistor thermally linked to the amplifier and being configured to sense a temperature at the amplifier, the temperature sensor circuit being a differential circuit having a first path and a second path with the first and second transistors being arranged on the first and second paths of the differential circuit respectively. The temperature sensor circuit is configured to generate an output voltage inversely proportional to a temperature difference between the ambient temperature and the temperature at the amplifier.

Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Abstract: A semiconductor die includes at least one electronic component. an at least partially moisture permeable material disposed on or about the at least one electronic component, at least one opening defining at least one path for moisture to migrate from an environment external to the die into the at least partially moisture permeable material, and a moisture impermeable shield disposed between the at least one electronic component and the at least one opening.

Abstract: Peak voltage limiting circuits and method for power amplifiers. A power amplifier and/or a voltage limiting circuit includes a diode circuit coupled to an output of an amplification stage, the diode circuit configured to provide a conductive path from the output when an output voltage exceeds a selected value. The power amplifier and/or voltage limiting circuit also includes a sink circuit coupled to the diode circuit and a bias circuit, the sink circuit configured to reduce a bias voltage provided by the bias circuit when the output voltage exceeds the selected value to thereby limit the output voltage.

Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Abstract: A semiconductor die includes at least one electronic component. an at least partially moisture permeable material disposed on or about the at least one electronic component, at least one opening defining at least one path for moisture to migrate from an environment external to the die into the at least partially moisture permeable material, and a moisture impermeable shield disposed between the at least one electronic component and the at least one opening.

Abstract: Peak voltage limiting circuits and method for power amplifiers. A power amplifier and/or a voltage limiting circuit includes a diode circuit coupled to an output of an amplification stage, the diode circuit configured to provide a conductive path from the output when an output voltage exceeds a selected value. The power amplifier and/or voltage limiting circuit also includes a sink circuit coupled to the diode circuit and a bias circuit, the sink circuit configured to reduce a bias voltage provided by the bias circuit when the output voltage exceeds the selected value to thereby limit the output voltage.

Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Abstract: Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 ?m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Abstract: Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 ?m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

Abstract: Provided herein are apparatus and methods for protecting radio frequency (RF) amplifiers from overdrive. In certain configurations, an RF amplification system includes a plurality of RF amplification stages including a first amplification stage and a second amplification stage subsequent to the first amplification stage in a signal path. The first amplification stage includes a first stage field-effect transistor (FET), and the second amplification stage includes a second stage FET and a gate-to-drain feedback circuit electrically connected between a gate and a drain of the second stage FET. The RF amplification system further includes an overdrive detection circuit that senses a drain current of the first stage FET to detect when an overdrive condition is present, and that decreases an impedance of the gate-to-drain feedback circuit in response to detection of the overdrive condition such that a gain of the second stage FET is reduced.

Abstract: Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Abstract: Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 ?m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level.

Abstract: Provided herein are apparatus and methods for protecting radio frequency (RF) amplifiers from overdrive. In certain configurations, an RF amplification system includes a plurality of RF amplification stages including a first amplification stage and a second amplification stage subsequent to the first amplification stage in a signal path. The first amplification stage includes a first stage field-effect transistor (FET), and the second amplification stage includes a second stage FET and a gate-to-drain feedback circuit electrically connected between a gate and a drain of the second stage FET. The RF amplification system further includes an overdrive detection circuit that senses a drain current of the first stage FET to detect when an overdrive condition is present, and that decreases an impedance of the gate-to-drain feedback circuit in response to detection of the overdrive condition such that a gain of the second stage FET is reduced.

Abstract: Provided herein are apparatus and methods for overdrive protection of radio frequency (RF) amplifiers. In certain configurations, an RF amplifier includes a plurality of amplification stages and an overdrive detection circuit. The overdrive detection circuit determines whether or not the RF amplifier is in an overdrive condition based on a current of an input amplification stage. Additionally, when the overdrive detection circuit detects an overdrive condition, the overdrive detection circuit controls an impedance of one or more feedback circuits of one or more amplification stages subsequent to the input amplification stage in a signal path of the RF amplifier to reduce the RF amplifier's gain. The overdrive protection schemes herein can be used to limit large current and voltage swing conditions manifesting within amplification transistors of the RF amplifier.

Abstract: Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 ?m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level.