Patents by Inventor Anthony K. Stamper

Anthony K. Stamper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Planar cavity MEMS and related structures, methods of manufacture and design structures
    Patent number: 11021364
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Russell T. Herrin, Jeffrey C. Maling, Anthony K. Stamper
  • VERTICAL FIELD EFFECT TRANSISTOR (FET)
    Publication number: 20210159336
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Inventors: Anthony K. STAMPER, Aaron L. VALLETT, Steven M. SHANK, John J. ELLIS-MONAGHAN
  • PHOTODETECTORS WITH A LATERAL COMPOSITION GRADIENT
    Publication number: 20210151621
    Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 20, 2021
    Inventors: Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Ellis-Monaghan, John J. Pekarik
  • Photodiodes integrated into a BiCMOS process
    Patent number: 11004878
    Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • TIGHT PITCH WIRINGS AND CAPACITOR(S)
    Publication number: 20210134716
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 6, 2021
    Inventors: Anthony K. STAMPER, Daisy A. VAUGHN, Stephen R. BOSLEY, Zhong-Xiang HE
  • MULTI-DEPTH REGIONS OF HIGH RESISTIVITY IN A SEMICONDUCTOR SUBSTRATE
    Publication number: 20210111063
    Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: Steven M. Shank, Anthony K. Stamper, Siva P. Adusumilli, Ian McCallum-Cook, Michel J. Abou-Khalil
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH EMITTER BASE JUNCTION OXIDE INTERFACE
    Publication number: 20210104621
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Vibhor JAIN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • COMPLEMENTARY TRANSISTOR STRUCTURES FORMED WITH THE ASSISTANCE OF DOPED-GLASS LAYERS
    Publication number: 20210098612
    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.
    Type: Application
    Filed: February 7, 2020
    Publication date: April 1, 2021
    Inventors: John J. Pekarik, Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, Herbert Ho, Qizhi Liu
  • Heterojunction bipolar transistors with stress material for improved mobility
    Patent number: 10964796
    Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo
  • METHODS OF FORMING A TRANSISTOR DEVICE WITH SOURCE/DRAIN REGIONS COMPRISING AN INTERFACE LAYER THAT COMPRISES A NON-SEMICONDUCTOR MATERIAL
    Publication number: 20210083111
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: John J. Pekarik, Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John Ellis-Monaghan
  • VERTICALLY STACKED FIELD EFFECT TRANSISTORS
    Publication number: 20210074730
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Anthony K. STAMPER, Steven M. SHANK, Siva P. ADUSUMILLI, Michel J. ABOU-KHALIL
  • BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
    Publication number: 20210074577
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.
    Type: Application
    Filed: November 2, 2020
    Publication date: March 11, 2021
    Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
  • Method of manufacturing MEMS switches with reduced switching voltage
    Patent number: 10941036
    Abstract: An approach includes a method of fabricating a switch. The approach includes forming a first cantilevered electrode, forming a second cantilevered electrode over an electrode and operable to contact the first cantilevered electrode upon an application of a voltage to the electrode, and forming an arm on the first cantilevered electrode with an extending protrusion extending upward from an upper surface of the arm.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen E. Luce, Anthony K. Stamper
  • SEMICONDUCTOR STRUCTURES INCLUDING STACKED DEPLETED AND HIGH RESISTIVITY REGIONS
    Publication number: 20210066118
    Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Michel J. Abou-Khalil, Aaron Vallett, Steven M. Shank, Bojidha Babu, John J. Ellis-Monaghan, Anthony K. Stamper
  • DUAL THICKNESS FUSE STRUCTURES
    Publication number: 20210066194
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: John J. PEKARIK, Anthony K. STAMPER, Vibhor JAIN
  • PHOTODIODES INTEGRATED INTO A BICMOS PROCESS
    Publication number: 20210057462
    Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 25, 2021
    Inventors: Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • Temperature-sensitive bias circuit
    Patent number: 10931274
    Abstract: One illustrative device includes, among other things, an active device comprising a first terminal, a first bias resistor connected to the first terminal, and a first resistor comprising a first phase transition material connected in parallel with the first bias transistor, wherein the first phase transition material exhibits a first low conductivity phase for temperatures less than a first phase transition temperature and a first high conductivity phase for temperatures greater than the first phase transition temperature.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 23, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain
  • SOI wafers with buried dielectric layers to prevent CU diffusion
    Patent number: 10923427
    Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Mukta G. Farooq, John A. Fitzsimmons
  • FIN-TYPE FIELD-EFFECT TRANSISTORS OVER ONE OR MORE BURIED POLYCRYSTALLINE LAYERS
    Publication number: 20210043624
    Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Siva P. Adusumilli, Julien Frougier, Ruilong Xie, Anthony K. Stamper
  • Heterojunction bipolar transistor with emitter base junction oxide interface
    Patent number: 10916642
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Steven M. Shank, John J. Pekarik