Abstract: A dipstick device with an integral wiper system is provided which comprises a wiping button which automatically resets the mechanism after actuating switch (i.e., a button) is pressed down to release a spring loaded dipstick tube guide which in turn moves in an upward direction to expose the dipstick to an elastomeric wiping assembly which wipes the dipstick as the dipstick is withdrawn from the dipstick tube guide.

Abstract: A shielded electrical connector for use in connecting a high voltage cable to a high voltage bushing has a receptacle at one end of the connector for receiving the bushing, a contact for connection to the bushing and a shield construction which includes a conductive sleeve at the one end of the connector and extending circumferentially around the receptacle, the sleeve extending axially along the connector and being electrically separated from the remainder of the shield such that upon energization the electrical potential difference between the contact and the sleeve is less than the electrical potential difference between the contact and the remainder of the shield.

Abstract: This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a "zero" level of a cell and also leave a precharged "one" level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.

Abstract: This disclosure relates to memory array organization of single transistor cells and the differential sense amplifiers provided therewith. To accommodate the differential sense amplifiers, the array is laid out in rows and functional columns where a functional column consists of a pair of columns such that odd row cells are connected to the odd column of the pair and even row cells are connected to the even column of the pair. A differential sense amplifier is then provided for each pair of odd and even columns which are inherently balanced at the sense amplifier terminals. Single ended or edge ended I/O circuitry is provided with direct access to the respective pairs of columns.