Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

Abstract: The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.

Abstract: A circuit for controlling two power transistors (24, 26) used an synchronous rectifiers in the secondary side of a switched mode power supply is provided. Current detector circuits (40, 42) measure current through parasitic diodes (28, 30) of the power transistors. It is shown that the synchronisation achieved is more accurate, and the resultant device is simpler and cheaper than previous solutions.

Abstract: A flyback-type switched current regulator, comprising first and second coupled windings and a circuit for connecting the first winding to a voltage source as soon as the windings are demagnetized. The regulator further comprises a current sensor that senses the current flowing through the first winding; a switch that disconnects the first winding from the voltage source when the first current in the first winding reaches a reference value, whereby the first winding is switched according to a duty cycle; and a circuit that varies the reference value in accordance with the duty cycle.

Abstract: A semiconductor component for switching an inductive load, comprises first and second external terminals, first and second control terminals and a node. A vertical bipolar transistor has a base region and is disposed between the first external terminal and the node. A first vertical transistor is disposed between the node and the second external terminal. A zener diode and a second vertical transistor are connected parallel between the base and the node.

Abstract: A circuit protects a power transistor of the vertical MOS or IGTB-type during the off state against forward overvoltages. The protection circuit includes a first circuit for limiting the voltage across the transistor to a predetermined voltage, lower than the forward breakdown voltage of the power transistor, a circuit for detecting the quantity of energy dissipated in the transistor when the first circuit is enabled, and a second circuit for turning the transistor on at low impedance. The second circuit is enabled when the detection circuit has detected that the dissipated energy has exceeded a predetermined energy threshold.

Abstract: A circuit for the detection of an open load for a power MOS transistor is designed to operate in a switching mode. The MOS transistor is partitioned into two transistors disposed in parallel. The second transistor has a resistance in the conductive state higher than the first transistor. The circuit includes circuitry for enabling only the second transistor when the current is within a low value range, and circuitry for detecting an open load when the circuit is operating within the low current range.

Abstract: A dynamic isolation circuit belonging to a monolithic integrated circuit comprising lateral transistors and vertical transistors. The lateral transistors are isolated by an isolating region connected to an isolating potential (V.sub.iso), these lateral transistors being connected up to voltages of a first polarity relative to a reference voltage (GND), the power terminal connected up to the rear face normally being at a potential (V.sub.out) of the first polarity relative to the reference voltage.

Abstract: An active diode for protecting from reverse voltages a monolithic structure comprising a logic portion and a power portion of the vertical MOS transistor type. The logic portion is constituted by conventional MOS transistors (TL-1) placed in a well (b 64) of a first conductivity type formed in a substrate (60) of the second conductivity type, the rear surface (74) of the substrate corresponding to the drain of the vertical MOS transistor. The active diode comprises a MOS transistor (TS), the gate of which (65) is controlled by a voltage whose sign is representative of the supply voltage polarity, the drain region of which (67) is grounded, and a highly doped deep area (71) of the first conductivity type extending from the upper surface (69) of the well (64), said area being connected to the source (66) of the MOS transistor.

Abstract: A stabilized bias generator supplies a threshold voltage to a MOS transistor fabricated on a common integrated circuit device. The bias generator automatically compensates for changes in the threshold voltage of the MOS transistor caused by varying operating parameters, changes in temperature or manufacturing parameters. A first comparator of a matched pair of comparators receives a biasing voltage and includes first and second inputs respectively receiving a variable voltage and a reference voltage. The second comparator of the matched pair has first and second inputs interconnected to receive the reference voltage. One of a pair of matched inverters has in input receiving an output from the first comparator and supplies at an output thereof the threshold voltage and the MOS transistor. The other of the matched pair of inverters is connected to receive an output from the second comparator.

Abstract: A gate control circuit for a power MOS transistor (1), the first main electrode (D) of which is connected to a high voltage (V.sub.CC) through a load (L), the second main electrode (S) of which is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V.sub.DD), comprises a switch (S1) for connecting at the switching ON of the power MOS transistor its first main electrode to its gate.