Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment

Abstract: An antenna tuner includes a control core, a switch logic coupled to the control core, the switch logic comprising a variable off-capacitance, and an electrical coupling coupled to the switch logic, the electrical coupling configured to connect the switch logic to an antenna system.

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

Abstract: An antenna tuner includes a control core, a switch logic coupled to the control core, the switch logic comprising a variable off-capacitance, and an electrical coupling coupled to the switch logic, the electrical coupling configured to connect the switch logic to an antenna system.

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment

Abstract: A seal ring includes a first continuous portion having an input terminal and an output terminal. The first continuous portion is configured to operate as an inductor. The seal ring further includes a second portion between the input terminal and the output terminal. The second portion is disconnected from the first continuous portion.

Abstract: An antenna tuning circuit achieves robust performance in a closed loop antenna tuning system due to the addition of protection circuits. In one instance, a protection circuit to detect an overload condition based on a threshold value may be included in the antenna tuning circuit. The antenna tuning circuit also includes a protection state register coupled to the protection circuit to store one or more safe states of operation to which the circuit is restored in response to detecting the overload condition. The antenna tuning circuit also includes a bus interface coupled to the protection state register to transmit an indication of a state of operation of the circuit to an external tuning control device coupled to the circuit and to receive pre-defined protection actions from the external tuning control device in response to the indication of the state of operation.

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.