Abstract: A method of forming sub-resolution features that includes: exposing a photoresist layer formed over a substrate to a first ultraviolet light (UV) radiation having a first wavelength of 365 nm or longer through a mask configured to form features at a first critical dimension, the photoresist layer including first portions exposed to the first UV radiation and second portions unexposed to the first UV radiation after exposing with the first UV radiation; exposing the first portions and the second portions to a second UV radiation; and developing the photoresist layer after exposing the photoresist layer to the second UV radiation to form the sub-resolution features having a second critical dimension less than the first critical dimension.

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

Abstract: A method of hybrid bonding includes accessing first dies sourced from a first wafer and second dies sourced from one or more second wafers. First overlay registration values (ORVs) of the first dies and second ORVs of the second dies are measured. A die pairing process is executed that matches the first dies with the second dies to form paired dies based on the first ORVs and the second ORVs. A hybrid bonding process is executed to bond the paired dies.

Abstract: Improved wafer chuck designs and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate during a puddle process. More specifically, the present disclosure provides various embodiments of wafer chucks that reshape a surface of a semiconductor substrate to ensure that the substrate surface is concave (or completely flat) before a processing liquid is dispensed onto the substrate surface to form a puddle of the processing liquid on the substrate surface. By providing the substrate surface with a concave (or completely flat) shape, the embodiments disclosed herein provide complete chemical coverage across the substrate surface during a puddle process, retain the puddle on the substrate surface and prevent the puddle from spilling over the substrate edge.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a heating device that is configured to generate a certain pattern of heat. The heating device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device can be applied to the semiconductor structure.

Abstract: A method for patterning a substrate, the method includes forming a first mask over the substrate, the first mask including first features and first spaces and exposing the substrate at a bottom of each first space; forming a second mask while retaining the first features, the second mask including second features and second spaces, the second features covering a portion of the substrate exposed by the first spaces; and either selectively depositing on or selectively removing material from the second features relative to the first features to change a width of each of the second features.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a light projection device that is configured to generate a certain pattern of light. The light projection device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of light generated by the light projection device is projected onto the semiconductor structure holding device and a corresponding certain pattern of heat is generated and transferred through the semiconductor structure holding device and applied to the semiconductor structure, in order to correct the shape and size of the semiconductor structure.

Abstract: Aspects of the present disclosure provide a method for correcting distortion of a semiconductor substrate. For example, the method can include receiving a semiconductor substrate with distortion, measuring the semiconductor substrate to identify the distortion in a plurality of positions on the semiconductor substrate, and implanting into the semiconductor substrate a lattice configuration signature according to the identified distortion in the positions such that the identified distortion of the semiconductor substrate is corrected.

Abstract: Improved wafer chuck designs, wet processing systems using such wafer chuck designs and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate during a puddle process. More specifically, the present disclosure provides various embodiments of wafer chucks that reshape a surface of a semiconductor substrate to ensure that the substrate surface is concave (or completely flat) before a processing liquid is dispensed onto the substrate surface to form a puddle of the processing liquid on the substrate surface. By providing the substrate surface with a concave (or completely flat) shape, the embodiments disclosed herein provide complete chemical coverage across the substrate surface during a puddle process, retain the puddle on the substrate surface and prevent the puddle from spilling over the substrate edge.

Abstract: Improved wafer chuck designs and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate during a puddle process. More specifically, the present disclosure provides various embodiments of wafer chucks that reshape a surface of a semiconductor substrate to ensure that the substrate surface is concave (or completely flat) before a processing liquid is dispensed onto the substrate surface to form a puddle of the processing liquid on the substrate surface. By providing the substrate surface with a concave (or completely flat) shape, the embodiments disclosed herein provide complete chemical coverage across the substrate surface during a puddle process, retain the puddle on the substrate surface and prevent the puddle from spilling over the substrate edge.

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

Abstract: A method includes receiving a first layout file for a first workpiece and a second layout file for a second workpiece. First layout file and second layout file are analyzed to identify contact points, which are grouped into bins. A contact point of a first bin is simulated using a simulation model. Contact point includes a first feature of the first workpiece and a second feature of the second workpiece. In response to determining that the contact point does not have desired properties, a first layout of the first feature and a second layout of the second feature are updated to determine an updated contact point. Updated contact point is simulated using the simulation model. In response to determining that the updated contact point has the desired properties, first layout file is updated to include updated first layout, and second layout file is updated to include updated second layout.

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

Abstract: A method of designing a standard cell layout includes determining a performance metric for the standard cell layout and executing an artificial intelligence (AI) algorithm. The executing of the AI algorithm includes extracting out a parameter of the standard cell layout having a different weighting with respect to optimizing the performance metric, adjusting the parameters of the standard cell layout, evaluating the performance metric based on the adjusted parameter of the standard cell layout, and continuing to adjust the one or more parameters until the performance metric reaches a desired value.

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.