Patents by Inventor Anton Devilliers

Anton Devilliers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180342410
    Abstract: Disclosed herein is a technology related to the amelioration (e.g., correction) of global wafer distortion based on a determination of localized distortions of a semiconductor wafer. Herein, a distortion is either an out-of-plane distortion (OPD) or in-plane distortion (IPD). The reference plane for this distortion is based on the plane shared by the surface of a presumptively flat semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: August 3, 2018
    Publication date: November 29, 2018
    Inventors: Joshua Hooge, Nathan Ip, Joel Estrella, Anton deVilliers
  • Publication number: 20180333680
    Abstract: A process is disclosed for wetting a filter cartridge used to treat a liquid solvent used in semiconductor manufacture. In the process, a filter cartridge having void spaces wherein the void spaces contain residual gas from the manufacturing process used to make the filter cartridge is connected to a source of purging gas. The purging gas is flowed through the filter cartridge to at least partially displace at least a portion of the residual gas from the manufacturing process used to make the filter cartridge. Next, liquid solvent is pumped through the filter cartridge so that the purging gas dissolves into the liquid solvent and to at least partially fill the void spaces to thereby at least partially wet out the filter cartridge with the liquid solvent.
    Type: Application
    Filed: July 27, 2017
    Publication date: November 22, 2018
    Inventors: Hoyoung Kang, Anton deVilliers, Corey Lemley
  • Publication number: 20180240802
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Application
    Filed: April 26, 2018
    Publication date: August 23, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton deVilliers
  • Patent number: 9997598
    Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 12, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton deVilliers, Nihar Mohanty, Subhadeep Kal, Kandabara Tapily
  • Publication number: 20180040695
    Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further Includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 8, 2018
    Inventors: Jeffrey Smith, Anton deVilliers, Nihar Mohanty, Subhadeep Kal, Kandabara Tapily
  • Publication number: 20180026042
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 25, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton deVilliers
  • Patent number: 9842965
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate in a liquid crystal device. Geometry of the textured surface provides a organization of a liquid crystal media.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 9718082
    Abstract: A fluid dispensing apparatus is disclosed. Systems include an in-line or linear bladder apparatus configured to expand to collect a charge of fluid, and contract to assist with fluid delivery and dispensing. During a dispense-off period process fluid can collect in this bladder after the process fluid is pushed through a fine filter (micro filter). A given filtration rate can be less than a dispense rate and thus the system herein compensates for filter-lag that often accompanies fluid filtering for microfabrication, while providing a generally linear configuration that reduces chances for defect creation.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Anton deVilliers, Ronald Nasman, James Grootegoed, Norman A. Jacobson, Jr.
  • Patent number: 9653315
    Abstract: A method of fabricating a substrate includes forming spaced first features over a substrate. An alterable material is deposited over the spaced first features and the alterable material is altered with material from the spaced first features to form altered material on sidewalls of the spaced first features. A first material is deposited over the altered material, and is of some different composition from that of the altered material. The first material is etched to expose the altered material and spaced second features comprising the first material are formed on sidewalls of the altered material. Then, the altered material is etched from between the spaced second features and the spaced first features. The substrate is processed through a mask pattern comprising the spaced first features and the spaced second features. Other embodiments are disclosed.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Scott Sills, Gurtej S. Sandhu, Anton deVilliers
  • Publication number: 20160315223
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 9385276
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 9281251
    Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: March 8, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A Fonseca, Anton Devilliers, Benjamen M Rathsack, Jeffrey T Smith, Lior Huli
  • Patent number: 9263297
    Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Tokyo Electron Limited
    Inventor: Anton deVilliers
  • Patent number: 9235134
    Abstract: Photolithographic apparatus and methods are disclosed. One such apparatus includes an optical path configured to provide a first diffraction pattern in a portion of an optical system and to provide a second diffraction pattern to the portion of the optical system after providing the first diffraction pattern. Meanwhile, one such method includes providing a first diffraction pattern onto a portion of an optical system, wherein a semiconductor article is imaged using the first diffraction pattern. A second diffraction pattern is also provided onto the portion of the optical system, but the second diffraction pattern is not used to image the semiconductor article.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: January 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Kaveri Jain, Lijing Gou, Zishu Zhang, Anton deVilliers, Michael Hyatt, Jianming Zhou, Scott Light, Dan Millward
  • Publication number: 20150349204
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 9176385
    Abstract: Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jianming Zhou, Scott L. Light, David Kewley, Prasanna Srinivasan, Anton deVilliers
  • Patent number: 9153458
    Abstract: A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Anton deVilliers
  • Patent number: 9112104
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Publication number: 20150214070
    Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 30, 2015
    Inventor: Anton deVilliers
  • Publication number: 20150209818
    Abstract: A fluid dispensing apparatus is disclosed. Systems include an in-line or linear bladder apparatus configured to expand to collect a charge of fluid, and contract to assist with fluid delivery and dispensing. During a dispense-off period process fluid can collect in this bladder after the process fluid is pushed through a fine filter (micro filter). A given filtration rate can be less than a dispense rate and thus the system herein compensates for filter-lag that often accompanies fluid filtering for microfabrication, while providing a generally linear configuration that reduces chances for defect creation.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 30, 2015
    Inventors: Anton deVilliers, Ronald Nasman, James Grootegoed, Norman A. Jacobson, JR.