Patents by Inventor Antonio Vellei
Antonio Vellei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230290827Abstract: A semiconductor device includes a transistor having macro cells. A plurality of the macro cells include a first macro cell and a second macro cell. Each first and second macro cell includes trenches formed in a first main surface of a semiconductor substrate. The trenches pattern the semiconductor substrate into mesas and include a conductive trench, with a conductive material in the conductive trench being electrically connected to a terminal. A majority of all trenches of the first macro cell exclusively run in a first direction. A majority of all trenches of the second macro cell exclusively run in a second direction different from the first direction. At least one first macro cell is arranged adjacent to at least one second macro cell.Type: ApplicationFiled: March 6, 2023Publication date: September 14, 2023Inventors: Antonio Vellei, Stefan Tophinke
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Publication number: 20230207673Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Inventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 11594621Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: GrantFiled: November 3, 2020Date of Patent: February 28, 2023Assignee: Infineon Technologies AGInventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 11581428Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.Type: GrantFiled: October 23, 2020Date of Patent: February 14, 2023Assignee: Infineon Technologies AGInventors: Alexander Philippou, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Patent number: 11469317Abstract: An RC IGBT includes, in an active region, an IGBT section and at least three diode sections. The arrangement of the diode sections obeys a design rule.Type: GrantFiled: March 16, 2021Date of Patent: October 11, 2022Assignee: Infineon Technologies Austria AGInventors: Frank Dieter Pfirsch, Erich Griebl, Viktoryia Lapidus, Anton Mauder, Christian Philipp Sandow, Antonio Vellei
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Publication number: 20210296479Abstract: An RC IGBT includes, in an active region, an IGBT section and at least three diode sections. The arrangement of the diode sections obeys a design rule.Type: ApplicationFiled: March 16, 2021Publication date: September 23, 2021Inventors: Frank Dieter Pfirsch, Erich Griebl, Viktoryia Lapidus, Anton Mauder, Christian Philipp Sandow, Antonio Vellei
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Patent number: 10978418Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.Type: GrantFiled: September 17, 2019Date of Patent: April 13, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
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Publication number: 20210082861Abstract: In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.Type: ApplicationFiled: November 6, 2020Publication date: March 18, 2021Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
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Patent number: 10930772Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.Type: GrantFiled: September 10, 2019Date of Patent: February 23, 2021Assignee: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Antonio Vellei
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Publication number: 20210050436Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: ApplicationFiled: November 3, 2020Publication date: February 18, 2021Inventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Publication number: 20210043759Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Alexander Philippou, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Patent number: 10910487Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.Type: GrantFiled: June 28, 2019Date of Patent: February 2, 2021Assignee: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
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Patent number: 10854739Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.Type: GrantFiled: April 1, 2020Date of Patent: December 1, 2020Assignee: Infineon Technologies AGInventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 10840362Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.Type: GrantFiled: October 23, 2018Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Publication number: 20200235232Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 10615272Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: GrantFiled: October 23, 2018Date of Patent: April 7, 2020Assignee: Infineon Technologies AGInventors: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 10608104Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.Type: GrantFiled: March 28, 2014Date of Patent: March 31, 2020Assignee: Infineon Technologies AGInventors: Alexander Philippou, Johannes Georg Laven, Christian Jaeger, Frank Wolter, Frank Pfirsch, Antonio Vellei
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Publication number: 20200013749Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
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Publication number: 20200006539Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Antonio Vellei
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Patent number: 10461056Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.Type: GrantFiled: May 22, 2017Date of Patent: October 29, 2019Assignee: Infineon Technologies AGInventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei