Patents by Inventor Antonio Vellei
Antonio Vellei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190319122Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Applicant: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
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Patent number: 10439055Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.Type: GrantFiled: March 29, 2018Date of Patent: October 8, 2019Assignee: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Antonio Vellei
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Patent number: 10347754Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.Type: GrantFiled: September 14, 2017Date of Patent: July 9, 2019Assignee: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
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Publication number: 20190123186Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Publication number: 20190123185Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 10224206Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recomType: GrantFiled: June 28, 2017Date of Patent: March 5, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Roman Baburske, Christian Jaeger, Franz Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
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Publication number: 20180286971Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.Type: ApplicationFiled: March 29, 2018Publication date: October 4, 2018Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Antonio Vellei
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Publication number: 20180076309Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.Type: ApplicationFiled: September 14, 2017Publication date: March 15, 2018Applicant: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
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Patent number: 9899504Abstract: A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.Type: GrantFiled: November 22, 2016Date of Patent: February 20, 2018Assignee: Infineon Technologies AGInventors: Roman Baburske, Johannes Georg Laven, Hans-Joachim Schulze, Antonio Vellei
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Publication number: 20180012764Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recomType: ApplicationFiled: June 28, 2017Publication date: January 11, 2018Inventors: Roman Baburske, Christian Jaeger, Franz Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
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Publication number: 20170338169Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.Type: ApplicationFiled: May 22, 2017Publication date: November 23, 2017Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
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Patent number: 9741571Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recomType: GrantFiled: March 25, 2016Date of Patent: August 22, 2017Assignee: Infineon Technologies AGInventors: Roman Baburske, Christian Jaeger, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
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Publication number: 20170148904Abstract: A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.Type: ApplicationFiled: November 22, 2016Publication date: May 25, 2017Inventors: Roman Baburske, Johannes Georg Laven, Hans-Joachim Schulze, Antonio Vellei
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Patent number: 9653568Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.Type: GrantFiled: June 9, 2015Date of Patent: May 16, 2017Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Alexander Philippou, Hans-Joachim Schulze, Christian Jaeger, Roman Baburske, Antonio Vellei
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Patent number: 9647100Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.Type: GrantFiled: October 20, 2015Date of Patent: May 9, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Christian Jaeger, Franz Josef Niedernostheide, Roman Baburske, Andre Rainer Stegner, Antonio Vellei
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Patent number: 9553179Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.Type: GrantFiled: January 31, 2014Date of Patent: January 24, 2017Assignee: Infineon Technologies AGInventors: Antonio Vellei, Johannes Georg Laven, Roman Baburske, Alexander Philippou
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Publication number: 20160284803Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recomType: ApplicationFiled: March 25, 2016Publication date: September 29, 2016Inventors: Roman Baburske, Christian Jaeger, Franz Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
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Publication number: 20160111528Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.Type: ApplicationFiled: October 20, 2015Publication date: April 21, 2016Inventors: Hans-Joachim Schulze, Christian Jaege, Franz Josef Niedernostheide, Roman Baburske, Andre Rainer Stegner, Antonio Vellei
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Patent number: 9263552Abstract: A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.Type: GrantFiled: June 5, 2014Date of Patent: February 16, 2016Assignee: Infineon Technologies AGInventor: Antonio Vellei
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Publication number: 20150357437Abstract: A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Inventor: Antonio Vellei