Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.

Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.