Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.