Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A plurality of blocks are connected together and selected for operations using a block select signal. A control circuit is configured to, after a read operation of memory cells of the block, hold a block select signal applied to a block select line to select a group of blocks having a same block select line at an on level. The control circuit can further discharge an unselected control gate in the group of blocks from a charged level to a lower level, lower than charged, prior to turning off the block select signal and charge the unselected control gate to a level greater than the lower level after the block select signal transitions from the on level to an off level.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.

Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.

Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.

Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.

Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element, wherein a loop number is incremented with each program-verify iteration includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when the loop number is less than a loop number threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the the loop number is greater than or equal to the loop number threshold corresponding to the target data state that the storage element is being programmed to.