Abstract: This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).

Abstract: Vertical junction field-effect transistors (VJFETs) with integrated source-drain anti-parallel diodes are described. In an embodiment, a trench VJFET with integrated source-drain anti-parallel diodes structure is coupled with a low-voltage metal oxide semiconductor field-effect transistor (MOSFET) in a dual gate cascode configuration.

Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: A chip stack assembly uses a monolithic metallic multilevel connector to both join connections on at different heights on the top sides at the of the chips, and to provide a large, robust connection surface on top of top of the assembly.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.

Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant.

Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.