Patents by Inventor Anup Bhalla

Anup Bhalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10333006
    Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Publication number: 20190115427
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 18, 2019
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Publication number: 20190088761
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Application
    Filed: October 5, 2018
    Publication date: March 21, 2019
    Inventors: Madhur Bobde, Lingpeng Guann, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20190043947
    Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.
    Type: Application
    Filed: July 26, 2018
    Publication date: February 7, 2019
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 10192982
    Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 29, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
  • Patent number: 10177221
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Publication number: 20180342626
    Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 29, 2018
    Inventors: Zhongda Li, Anup Bhalla
  • Publication number: 20180337274
    Abstract: Fabricating a semiconductor device includes: forming a first gate trench and a second gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the first gate trench to form a first gate and depositing gate material in the second gate trench to form a second gate; forming a body; forming a source; forming an active region contact trench that extends through the source and the body, and a gate contact trench within the second gate; forming an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; and disposing a first electrode within the active region contact trench and a second electrode within the gate contact trench.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Publication number: 20180323315
    Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 8, 2018
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 10121907
    Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 6, 2018
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Zhongda Li
  • Patent number: 10121857
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Publication number: 20180308967
    Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: October 25, 2018
    Inventors: Anup Bhalla, Tinggang Zhu
  • Patent number: 10103240
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: October 16, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guann, Anup Bhalla, Hamza Yilmaz
  • Patent number: 10074742
    Abstract: A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 11, 2018
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 10069005
    Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 4, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 10062755
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 28, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20180240872
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 23, 2018
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10056500
    Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 21, 2018
    Assignee: United Silicon Carbide, Inc.
    Inventors: Zhongda Li, Anup Bhalla
  • Patent number: 10050154
    Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 14, 2018
    Assignee: United Silicon Carbide, Inc.
    Inventors: Zhongda Li, Anup Bhalla
  • Patent number: 10050134
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 14, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho