Abstract: A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains

Abstract: A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.

Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.

Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.

Abstract: Example implementations described herein are directed to the generation of a specification for automatic power management of a network on chip and/or a system on chip. Such example implementations can include automatically generating a specification comprising at least one of a power domain, an always-on indicator, a voltage domain, a voltage level, and a clock frequency for each of one or more agents of a System on Chip (SoC) and a Network on Chip (NoC), the voltage domain indicative of power supply of the each agent, and the power domain indicative of one or more power switch rules applied to the each agent.