Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.

Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.

Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.

Abstract: Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.