Patents by Inventor Anup P. Jose

Anup P. Jose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10186208
    Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Anup P. Jose, Amir Amirkhany
  • Publication number: 20180197485
    Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 12, 2018
    Inventors: Anup P. Jose, Amir Amirkhany
  • Patent number: 7548094
    Abstract: Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 16, 2009
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Kenneth L. Shepard, Anup P. Jose