Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to memory devices and methods of manufacture. The structure includes: a gate structure having a gate dielectric material and a gate body; a body region under the gate dielectric material; a first doped region laterally adjacent to a first side of the body region; a second doped region laterally adjacent to the first doped region; and a shallow trench isolation structure laterally adjacent to a second side of the body region.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Abstract: A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.

Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

Abstract: A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.