Patents by Inventor Anupama

Anupama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250145807
    Abstract: The present invention discloses styrene butadiene rubber (SBR) composition containing the by-products based on renewable source such as calcium salt of lanolin fatty acid (CA), magnesium salt of lanolin fatty acids, pretreated calcium salt of lanolin fatty, lanolin fatty acids like crude (CLFA) and bleached lanolin fatty acids (BLFA) and process thereof.
    Type: Application
    Filed: February 11, 2023
    Publication date: May 8, 2025
    Inventors: Anupama DATLA, Prashant NAGRE, Jagdish TAMORE, Kishor AMBAWADE, Mohammad Kausar SHAIKH
  • Publication number: 20250145659
    Abstract: The present invention discloses a short, cost effective process for preparation of cholesterol from bisnoralcohol (BA).
    Type: Application
    Filed: February 11, 2023
    Publication date: May 8, 2025
    Inventors: Anupama DATLA, Prashant NAGRE, Jagdish TAMORE, Sachin Govind WADHAVANE, Amol SHIRSATH, Gajanan Subhash GAONKAR
  • Publication number: 20250142870
    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 1, 2025
    Inventors: Cory BOMBERGER, Anand S. MURTHY, Tahir GHANI, Anupama BOWONDER
  • Patent number: 12286454
    Abstract: The invention discloses an improved process for production of vitamin D3 from 7-dehydrocholesterol (7-DHC) and to a simple process for recovery unreacted 7-DHC for further reuse. The invention further describes a process for isolation and purification of Vitamin D3.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 29, 2025
    Assignee: FERMENTA BIOTECH LIMITED
    Inventors: Anupama Datla, Prashant Nagre, Jagdish Tamore, Sreenath Trivikram, Sachin Wadhavane
  • Patent number: 12279666
    Abstract: The present disclosure relates to a dual helmet that can be easily converted into two sets of helmets having protective cushioning, and which are comfortable, yet strong, safe, and up to the required standards. The helmet includes a first shell and a second shell defining a shell of a first helmet and a second helmet, respectively. The second shell is removably disposed over the first shell such that the helmet can be used as a single combine helmet when the shells are together, and further, the second shell can be separated from the first shell to form two separate helmets. The helmet includes a first cushion disposed within the first shell, and a second cushion for the second helmet being removably configured within the first cushion such that the second cushion can be separated by slightly bending it, and later can be configured with the second shell to form the second helmet and the first helmet, as required.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: April 22, 2025
    Inventors: Anupama Sethi, Arvind Sethi
  • Patent number: 12267257
    Abstract: Methods, systems and computer program products for deploying a virtualization system onto cloud computing infrastructure. Virtual machines of a virtualization system are deployed onto computing nodes that are interconnected via a cloud provider's networking infrastructure. When migrating a virtual machine from a source computing node to a target computing node that is also interconnected to the cloud provider's networking infrastructure, the addressing of the to-be-migrated virtual machine changes. Dynamically-updated media access control translation tables are maintained at the computing nodes. The media access control translation tables are populated with cloud provider media access control addresses received from the cloud provider. A virtual switch at each computing node modifies incoming and outgoing packets of a to-be-migrated virtual machine based on contents of that node's media access control translation table.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 1, 2025
    Assignee: Nutanix, Inc.
    Inventors: Nitin Parab, Aaron Dean Brown, Anupama Ashok Lolage, Binny Sher Gill, Blinston Savio Fernandes
  • Patent number: 12242900
    Abstract: Techniques are disclosed for providing method for providing an event timer for event synchronization across Kubernetes clusters. The event timer is configured to provide event synchronization on behalf of microservice instances in the cloud computing environment. In response to a request for an event timer for a timed event, it is determined whether the requested event timer has been started for a second microservice instance. If the requested event timer has been started, a state of the requested event timer is sent to the first microservice instance If the requested event timer has not been started, the requested event timer is instantiated, and a state of the instantiated event timer is stored in a database. The instantiated event timer is independent of the first and second microservice instances. In response to an expiration of the event timer, a single callback for processing of the event is generated.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 4, 2025
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Kunal Anand Ekawde, Abhay Balappanavar, Michael Anthony Brown, Ronald Mark Parker, Anupama Raghavan, Dhananjaya Eadala, Rama Krishna Prasad Mangalaparthi, Mark Gordon Libby
  • Patent number: 12237420
    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Anand S. Murthy, Tahir Ghani, Anupama Bowonder
  • Publication number: 20250059538
    Abstract: Provided are compositions and methods for silencing suppressor tRNAs. Further provided are compositions and methods for silencing suppressor tRNAs during AAV production for producing virions comprising sequences coding for suppressor tRNAs.
    Type: Application
    Filed: December 23, 2022
    Publication date: February 20, 2025
    Inventors: Sandhya Pande, Anupama Lakshmanan, Lauriel Earley, Stephen Michael Burleigh, Collin Hauskins, Adrian Wrangham Briggs, Kevin Stein
  • Patent number: 12224940
    Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Malek Musleh, Gene Wu, Anupama Kurpad, Allister Alemania, Roberto Penaranda Cebrian, Robert Southworth, Pedro Yebenes Segura, Curt E. Bruns, Sujoy Sen
  • Patent number: 12210395
    Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: January 28, 2025
    Assignee: Intel Corporation
    Inventors: Anupama Suryanarayanan, Avinash N. Ananthakrishnan, Chinmay Ashok, Jeremy J. Shrall
  • Patent number: 12209268
    Abstract: Hybrid gas vesicle gene cluster (GVGC) configured for expression in a prokaryotic host are described comprising gas vesicle assembly (GVA) genes native to a GVA prokaryotic species and capable of being expressed in a functional form in the prokaryotic host, and one or more gas vesicle structural (GVS) genes native to one or more GVS prokaryotic species, at least one of the one or more GVS prokaryotic species different from the GVA prokaryotic species, and related gas vesicle reporting (GVR) genetic circuits, genetic, vectors, engineered cells, and related compositions methods and systems to produce GVs, hybrid GVGC and/or image a target site.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: January 28, 2025
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Raymond W. Bourdeau, Anupama Lakshmanan, Arash Farhadi, Mikhail G. Shapiro, Audrey Lee-Gosselin
  • Patent number: 12211081
    Abstract: Methods and systems for providing a product bundle recommendation are disclosed. One method includes receiving a selection of a first product. Data relating to historical customer shopping activity and data describing online shopping sessions in which products are selected for addition to historical shopping carts to which the first product was previously added is accessed. A list bundled products having a complementary relationship with the first product is generated. At least one product from the list of bundled products is selected and the at least one product is presented on a user interface on a customer device as a recommendation for purchase with the first product. A filter may be applied to the list of bundled products, such as a price filter. The method may be performed by a system including one or more computing devices communicating via a network with one or more data storage devices.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 28, 2025
    Assignee: Target Brands, Inc.
    Inventors: Aparupa Das Gupta, Anupama Joshi, Gregory Olsen, Saloni Agarwal
  • Patent number: 12205061
    Abstract: A method for developing or improving a process for producing a product from a material comprising steps of acquiring the composition for at least two slurries as raw material data (17) for the CMP based manufacturing process and its relevant parameters (2) by using a Data Collecting computer (9); physically performing specific method steps of a CMP process; measuring relevant parameters of the used slurries and the physically performed CMP process to determine the CMP process performance by using the Data Collecting computer (9); analyzing the measured data about the relevant parameters with a specific software performed on an Analyzing computer (11) by creating for the software and applying with it a predictive model using Machine Learning to understand the intercorrelation of the different parameters and using the results to improve the CMP process performance and the resulting product quality of the CMP based manufacturing process.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: January 21, 2025
    Assignee: Versum Materials US, LLC
    Inventors: Cesar Clavero, Vid Gopal, Ryan Clarke, Esmeralda Yitamben, Hieu Pham, Anupama Mallikarjunan, Rung-Je Yang, Shirley Lin, Hongjun Zhou, Joseph Rose, Krishna Murella, Lu Gan
  • Publication number: 20250006234
    Abstract: Some embodiments include input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage of the latch coupled to the memory node and including an output node to provide output data information based on the information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Ganesan Iyer, Anupama A. Thaploo, Ananthakrishnan Ponnileth Rajendran
  • Publication number: 20250005851
    Abstract: Systems and techniques are described herein for generating models of faces. For instance, a method for generating models of faces is provided. The method may include obtaining one or more images of one or both eyes of a face of a user; obtaining audio data based on utterances of the user; and generating, using a machine-learning model, a three-dimensional model of the face of the user based on the one or more images and the audio data.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Arpit BHATNAGAR, Chiranjib CHOUDHURI, Anupama S, Avani RAO, Ajit Deepak GUPTE
  • Publication number: 20250006733
    Abstract: Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: Swapnadip GHOSH, Chiao-Ti HUANG, Amritesh RAI, Akitomo MATSUBAYASHI, Fariha KHAN, Anupama BOWONDER, Reken PATEL, Chi-Hing CHOI
  • Publication number: 20240428105
    Abstract: One or more systems, computer program products and/or computer-implemented methods of use provided herein relate to a process to generate an ansatz-hardware pairing. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise a machine learning model that compares inputs to a database of stored ansatz-hardware pairings and that generates the ansatz-hardware pairing based on the comparing, wherein the inputs comprise desired ansatz metrics, defining a variational quantum algorithm, and hardware metrics of quantum hardware available to operate a quantum circuit defined by the ansatz, and a generating component that determines a prediction comprising the ansatz-hardware pairing, wherein the prediction comprises a predicted accuracy of an output of the quantum circuit to be performed on the quantum hardware of the ansatz-hardware pairing.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Inventors: Anupama RAY, Kalyan DASGUPTA, SheshaShayee K RAGHUNATHAN, Dhinakaran VINAYAGAMURTHY, Dhiraj MADAN
  • Patent number: 12163224
    Abstract: Described herein are methods for forming a conformal Group 4, 5, 6, 13 metal or metalloid doped silicon nitride film. In one aspect, there is provided a method of forming an aluminum silicon nitride film comprising the steps of: providing a substrate in a reactor; introducing into the reactor an at least one aluminum precursor which reacts on at least a portion of the surface of the substrate to provide a chemisorbed layer; purging the reactor with a purge gas; introducing into the reactor an organoaminosilane precursors to react on at least a portion of the surface of the substrate to provide a chemisorbed layer; introducing a nitrogen source and an inert gas into the reactor to react with at least a portion of the chemisorbed layer; and optionally purge the reactor with an inert gas; and wherein the steps are repeated until a desired thickness of the aluminum nitride film is obtained.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 10, 2024
    Assignees: VERSUM MATERIALS US, LLC, BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Xinjian Lei, Moo-Sung Kim, Anupama Mallikarjunan, Aaron Michael Dangerfield, Luis Fabián Peña, Yves Jean Chabal
  • Patent number: 12147519
    Abstract: Systems and techniques are provided for performing user authentication. For example, a process can include obtaining a plurality of images associated with a face and a facial expression of the user, wherein each respective image of the plurality of images includes a different portion of the face. An encoder neural network can be used to generate one or more predicted three-dimensional (3D) facial modeling parameters, wherein the encoder neural network generates the one or more predicted 3D facial modeling parameters based on the plurality of images. A reference 3D facial model associated with the face and the facial expression can be obtained. An error can be determined between the one or more predicted 3D facial modeling parameters and the reference 3D facial model, and the user can be authenticated user based on the error being less than a pre-determined authentication threshold.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: November 19, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Anupama S, Chiranjib Choudhuri, Avani Rao, Ajit Deepak Gupte