Patents by Inventor Aomar Halimaoui

Aomar Halimaoui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8906776
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Publication number: 20140284769
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann
  • Publication number: 20130273440
    Abstract: A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other.
    Type: Application
    Filed: December 12, 2011
    Publication date: October 17, 2013
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Pascale Mazoyer, Aomar Halimaoui
  • Publication number: 20130264678
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 8536027
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Publication number: 20120225326
    Abstract: A module of a biofuel cell includes three module elements each having a porous membrane. At least two of the porous membranes are electrically conducting and form the cathode and the anode of the biofuel cell. The third membrane, which is preferably positioned between the two electrically conducting membranes need not be conducting, but defines two emergent cavities within the module. A porous through-channel extends through a silicon support of the module so as to connect one of the emergent cavities to at least one external wall of the silicon support.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS S.A.
    Inventors: Richard Fournel, Aomar Halimaoui
  • Publication number: 20120161292
    Abstract: A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 28, 2012
    Inventors: Aomar Halimaoui, Marc Zussy
  • Patent number: 8178426
    Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: May 15, 2012
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Yves Morand, Yves Campidelli, Olivier Kermarrec
  • Publication number: 20120094470
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 19, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Publication number: 20100320567
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 23, 2010
    Applicants: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Aomar HALIMAOUI, Rebha EL FARHANE, Benoit FROMENT
  • Publication number: 20100289123
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Application
    Filed: September 26, 2008
    Publication date: November 18, 2010
    Applicant: ST Microelectronics (Crolles) 2 SAS
    Inventor: Aomar Halimaoui
  • Patent number: 7781296
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: August 24, 2010
    Assignees: STMicroelectronics SAS, Koninklijke Philips Electronics N.V.
    Inventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment
  • Patent number: 7638844
    Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: December 29, 2009
    Assignees: STMicroelectronics S.A., Commissariat à l'énergie atomique
    Inventors: Stéphane Monfray, Aomar Halimaoui, Philippe Coronel, Damien Lenoble, Claire Fenouillett-Beranger
  • Patent number: 7635615
    Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 22, 2009
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Jean-Charles Barbe, Sylvian Barraud, Claire Fenouillet-Beranger, Claire Gallon, Aomar Halimaoui
  • Patent number: 7569482
    Abstract: An integrated circuit is silicided by depositing at least one metal on a silicon-containing region and forming a metal silicide. Residue metal that has not been silicided during the formation of the metal silicide is then removed. The removal of the residue metal involves the conversion of the residue metal to an alloy containing the germanide of said metal with minimal if any adverse affect on the silicide. Next, the alloy is removed, in a manner selective to the silicide, by dissolving the alloy in a chemical solution.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: August 4, 2009
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Aomar Halimaoui
  • Publication number: 20080197447
    Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 21, 2008
    Applicants: STMicroelectronics S.A., STMicroelectronics Crolles 2 SAS
    Inventors: Aomar Halimaoui, Yves Morand, Yves Campidelli, Olivier Kermarrec
  • Publication number: 20080185681
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Application
    Filed: June 7, 2005
    Publication date: August 7, 2008
    Inventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment
  • Publication number: 20080087959
    Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.
    Type: Application
    Filed: March 2, 2007
    Publication date: April 17, 2008
    Applicants: STMicroelectronics S.A., Commissariat A L'energie Atomique
    Inventors: Stephane Monfray, Aomar Halimaoui, Philippe Coronel, Damien Lenoble, Claire Fenouillet-Beranger
  • Patent number: 7279404
    Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: October 9, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Publication number: 20070197029
    Abstract: An integrated circuit is silicided by depositing at least one metal on a silicon-containing region and forming a metal silicide. Residue metal that has not been silicided during the formation of the metal silicide is then removed. The removal of the residue metal involves the conversion of the residue metal to an alloy containing the germanide of said metal with minimal if any adverse affect on the silicide. Next, the alloy is removed, in a manner selective to the silicide, by dissolving the alloy in a chemical solution.
    Type: Application
    Filed: January 15, 2007
    Publication date: August 23, 2007
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Aomar Halimaoui