Patents by Inventor Aomar Halimaoui

Aomar Halimaoui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070001227
    Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 4, 2007
    Inventors: Jean-Charles Barbe, Sylvian Barraud, Claire Fenouillet-Beranger, Claire Gallon, Aomar Halimaoui
  • Publication number: 20060088988
    Abstract: A method for forming silicon-germanium in the upper portion of a silicon substrate, including the steps of: depositing a germanium layer doped at a concentration in dopant elements greater than 1019 atoms per cm3 on a silicon substrate; heating to have the germanium diffuse into the silicon substrate to form a doped silicon-germanium layer in the upper portion of the silicon substrate; and eliminating the germanium layer.
    Type: Application
    Filed: October 25, 2005
    Publication date: April 27, 2006
    Applicant: STMicroelectronics CROLLES 2 SAS
    Inventors: Aomar Halimaoui, Frederic Boeuf
  • Patent number: 6969661
    Abstract: A method for forming, in an integrated circuit, a localized region of a material difficult to etch, including the steps of forming a first silicon oxide layer having a thickness smaller than 1 nm on a silicon substrate; depositing, on the first layer, a second layer selectively etchable with respect to the first layer; forming in the second layer an opening according to the pattern of said localized region; selectively growing on the second layer, around the opening, a germanium layer, the material of the second layer being chosen to enable this selective growth, whereby there exists in the germanium an opening conformable with the above opening; depositing the material difficult to etch so that it does not deposit on the germanium; depositing a conductive layer to fill the opening in the germanium; performing a leveling to expose the germanium; and removing the germanium and the first and second layers.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 29, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Publication number: 20050085026
    Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 21, 2005
    Inventors: Stephane Monfray, Aomar Halimaoui, Philippe Coronel, Damien Lenoble, Claire Fenouillet-Beranger
  • Publication number: 20050037599
    Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.
    Type: Application
    Filed: July 1, 2004
    Publication date: February 17, 2005
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Publication number: 20050026457
    Abstract: A method for forming, in an integrated circuit, a localized region of a material difficult to etch, including the steps of forming a first silicon oxide layer having a thickness smaller than 1 nm on a silicon substrate; depositing, on the first layer, a second layer selectively etchable with respect to the first layer; forming in the second layer an opening according to the pattern of said localized region; selectively growing on the second layer, around the opening, a germanium layer, the material of the second layer being chosen to enable this selective growth, whereby there exists in the germanium an opening conformable with the above opening; depositing the material difficult to etch so that it does not deposit on the germanium; depositing a conductive layer to fill the opening in the germanium; performing a leveling to expose the germanium; and removing the germanium and the first and second layers.
    Type: Application
    Filed: December 23, 2003
    Publication date: February 3, 2005
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 6287936
    Abstract: The method is for forming porous silicon in a silicon substrate, in particular for improving the quality factor of an inductive circuit produced on a silicon semiconductor wafer which also incorporates integrated transistors. The rear face of the wafer, already incorporating the transistors and the inductive circuit on its front face, is placed in contact with an acid electrolyte containing hydrofluoric acid and at least one other acid. An anodic oxidation of the silicon of the wafer at the rear face is carried out so as to convert this silicon into porous silicon over a predetermined height from the rear face which is in contact with the electrolyte.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: September 11, 2001
    Assignees: STMicroelectronics S.A., France Telecom
    Inventors: Ernesto Perea, Guillermo Bomchil, Aomar Halimaoui
  • Patent number: 6177235
    Abstract: The present invention relates to an improved photolithography process particularly suitable for high-resolution optical lithography techniques using the g, h and i lines of the spectrum of mercury and short-wavelength UV, comprising, prior to deposition of the photosensitive resin on the layer of material to be lithographically patterned, the formation of an antireflective porous layer within the said layer to be lithographically patterned and on the surface of the latter.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: January 23, 2001
    Assignee: France Telecom
    Inventors: Jean Marc Francou, Aomar Halimaoui, Andr{acute over (e)} Schiltz