Abstract: A method includes mounting a ceramic phosphor on an acrylic-free and metal-containing catalyst-free tacky layer of a dicing tape, dicing the ceramic phosphor from the dicing tape into ceramic phosphor plates, removing the ceramic phosphor plates from the dicing tape, and attaching the ceramic phosphor plates on light-emitting device (LED) dies.

Abstract: A method includes mounting a ceramic phosphor on an acrylic-free and metal-containing catalyst-free tacky layer of a dicing tape, dicing the ceramic phosphor from the dicing tape into ceramic phosphor plates, removing the ceramic phosphor plates from the dicing tape, and attaching the ceramic phosphor plates on light-emitting device (LED) dies.

Abstract: In embodiments of the invention, a light emitting device includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A first wavelength converting layer is disposed in a path of light emitted by the light emitting layer. The first wavelength converting layer may be a wavelength converting ceramic. A second wavelength converting layer is fused to the first wavelength converting layer. The second wavelength converting layer may be a wavelength converting material disposed in glass.

Abstract: A method includes mounting a ceramic phosphor (102) on an acrylic-free and metal-containing catalyst-free tacky layer (108) of a dicing tape (104), dicing the ceramic phosphor (102) from the dicing tape (104) into ceramic phosphor plates (11)2, removing the ceramic phosphor plates (112) from the dicing tape (104), and attaching the ceramic phosphor plates (112) on light-emitting device (LED) dies.

Abstract: In embodiments of the invention, a light emitting device includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A first wavelength converting layer is disposed in a path of light emitted by the light emitting layer. The first wavelength converting layer may be a wavelength converting ceramic. A second wavelength converting layer is fused to the first wavelength converting layer. The second wavelength converting layer may be a wavelength converting material disposed in glass.

Abstract: A ceramic green wavelength conversion element (120) is coated with a red wavelength conversion material (330) and placed above a blue light emitting element (110) such that the ceramic element (120) is attached to the light emitting element (110), thereby providing an efficient thermal coupling from the red and green converters (330, 120) to the light emitting element (110) and its associated heat sink. To protect the red converter coating (330) from the effects of subsequent processes, a sacrificial clear coating (340) is created above the red converter element (330). This clear coating (340) may be provided as a discrete layer of clear material, or it may be produced by allowing the red converters to settle to the bottom of its suspension material, thereby forming a converter-free upper layer that can be subjected to the subsequent fabrication processes.

Abstract: A method includes mounting a ceramic phosphor (102) on an acrylic-free and metal-containing catalyst-free tacky layer (108) of a dicing tape (104), dicing the ceramic phosphor (102) from the dicing tape (104) into ceramic phosphor plates (11)2, removing the ceramic phosphor plates (112) from the dicing tape (104), and attaching the ceramic phosphor plates (112) on light-emitting device (LED) dies.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: A memory cell is provided that includes a steering element, a reversible resistance-switching element coupled to the steering element and a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element. The reversible resistance-switching element includes tantalum, and is formed using a selective deposition process. Numerous other aspects are provided.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (CNT) material above the first conductor; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: A memory cell is provided that includes a steering element, a reversible resistance-switching element coupled to the steering element and a silicide-forming metal layer disposed between the steering element and the reversible resistance-switching element. The reversible resistance-switching element includes tantalum, and is formed using a selective deposition process. Numerous other aspects are provided.

Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Abstract: Rewritable switching materials and methods for forming the same are described herein. One embodiment is a storage device comprising a first electrode, a state change element in contact with the first electrode, the state change element comprises ZrxYyOz, and a second electrode in contact with the state change element. A method for forming such a storage device is also disclosed herein. Another embodiment is a storage device comprising a first electrode a state change element in contact with the first electrode, the state change comprises at least one of cerium oxide or bismuth oxide, and a second electrode in contact with the state change element. A method for forming such a storage device is also disclosed herein.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.