Abstract: The subject matter disclosed herein relates to a system and method for receiving a plurality of signals generated by a plurality of sensors adapted to detect physical movement of a mobile device with respect to a plurality of coordinate axes. A time at which at least one of the received signals is digitized is delayed to provide an output of digitized versions of the received plurality of signals synchronized with respect to a common point in time.

Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Abstract: A method and apparatus for receiving video signals from a plurality of video cameras, such as in a video surveillance system. The video cameras are each coupled to provide a video signal to a respective input of a multiplexer. The multiplexer routes a selected one of the video signals to a video decoder. The video decoder receives the selected video signal and is conditioned according to the video signal. This includes synchronizing the video decoder to a frequency and phase of the video signal, controlling a gain level for the video signal and adjusting a dc clamping level for dc restoration of the video signal. Parameters representative of each of these quantities are stored in association with the identity of the corresponding video camera. The video decoder also places each video signal into a format suitable for storage in a storage device and for display by a display device.

Abstract: A line driver couples a data transceiver to a transmission line having a load impedance Z via a transformer with a turns ratio of 1:n, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range different from the first frequency range. The line driver includes an input port for receiving an input signal voltage, an output port for supplying an output signal voltage to the transformer, and a differential amplifier having a low pass filter for amplifying the input signal voltage and outputting an amplified signal voltage. The line driver further includes termination resistors having a resistance Rt, where R t = Z 2 ? n 2 × k ( 0 < k ? 1 ) , and a positive feedback path for coupling the output signal voltage from the output port to an appropriate node of the differential amplifier so that a synthesized output impedance substantially matches the load impedance Z over the second frequency range.

Abstract: A circuit dynamically biases switching elements in a current-steering digital-to-analog converter (DAC), The DAC includes, in each cell, a current source coupled to a current node, a first switching element coupled between the current node and a first DAC output node, and a second switching element coupled between the current node and a second DAC output node. The circuit includes first and second inputs coupled to the first and second DAC output nodes, respectively, first and second outputs coupled to the first and second switching elements, respectively, and a third output coupled to the first and second switching elements. The first and second outputs provide a first ON bias voltage and a second ON bias voltage to control the first and second switching elements, respectively, such that a voltage at the current node is maintained at a predetermined voltage. The third output provides a common OFF bias voltage.

Abstract: A method and apparatus control switching noise in a digital-to-analog interface in a mixed-signal circuit. The digital-to-analog interface includes a first plurality (K) of switching elements and a second plurality (M) of dummy switching elements, the second plurality (M) being smaller than the first plurality (K). The switching noise control includes (a) receiving a digital data signal, (b) determining a number (N) of the switching elements to be switched for the digital data signal, and (c) switching the second plurality (M) less the number (N) of the dummy switching elements simultaneously with switching the number (N) of the switching elements.

Abstract: A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving a receive signal from the transformer. The transformer includes a first port coupled to the transmission line, a second port coupled to the driver circuit, a third port coupled to the receiver circuit, a first winding part having a turns ratio of 1: n, where n>1, for coupling the transmit signal from the second port to the first port, and a second winding part having a turns ratio of 1: m, where m<n, for coupling the receive signal from the first port to the third port.

Abstract: A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting the time shift into an equivalent phase shift and sending a corresponding phase correction number to a waveform generator block to correct the time shift, and thus stabilize subcarrier generation.

Abstract: A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.

Abstract: A method and circuit control a quiescent current of an amplifier including a preamplifier, error amplifiers, and output devices driven by the error amplifiers, the error amplifiers having an input-referred offset voltage. The method includes (a) applying a calibration voltage to an input of the error amplifiers, (b) calibrating a quiescent current of the output devices by changing the calibration voltage so that the calibrated quiescent current has a predetermined current value, the calibration voltage corresponding to the calibrated quiescent current being set as a correction voltage, and (c) operating the amplifier with the correction voltage applied to the input of the error amplifiers. The circuit includes a correction voltage generator supplying a correction voltage to the error amplifier input, a quiescent current detector detecting the quiescent current, and a calibration circuit adjusting the correction voltage so that the quiescent current is calibrated to a predetermined current value.

Abstract: A dynamic supply control circuit is provided for a line driver. The line driver has an amplification factor G, receives an input signal voltage, and drives a transmission line having a load RL via a transformer having a turns ratio of 1:n. The circuit includes an input node for receiving an input signal voltage, a supply node for supplying a driving voltage to the line driver, a lift diode coupled between a fixed supply voltage and the supply node, a lift capacitor coupled between the supply node and an output node, and a lift amplifier having the amplification factor G coupled between the input node and the output node. The lift amplifier drives the lift capacitor when the input signal voltage is greater than an input threshold voltage, the input threshold voltage having a value greater than a common mode voltage of the input signal voltage.

Abstract: A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting the time shift into an equivalent phase shift and sending a corresponding phase correction number to a waveform generator block to correct the time shift, and thus stabilize subcarrier generation.