Abstract: Systems and methods are disclosed for open block refresh management. In certain embodiments, an apparatus may comprise a circuit configured to monitor an amount of time a block of a solid-state memory remains in an open state where the block has not been fully filled with data, and in response to reaching an open block time limit, compare an amount of the block already written with data against a threshold amount. When less than a threshold amount of the block has been written with data, the circuit may refresh data from a last N pages from the block by writing the data to a new location, N being a number of pages less than all pages in the block. When more than the threshold amount of the block has been written with data, the circuit may fill a remaining unwritten amount of the block with dummy data.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: A circuit may be configured to adaptively combine two or more waveforms into a single waveform. The circuit can generate weighting factors based on received error signals, and can apply the weighting factors to the two or waveforms to be combined. In some examples, a circuit can be configured to receive input signals, receive error signals, generating a weighting coefficient based on at least some of the error signals, and determine an output signal based on the weighting coefficient and the input signals.

Abstract: Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.

Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.

Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.

Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.

Abstract: Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: A coding device, such as a memory device or communication system, comprising encoder circuitry configured to encode data into inner codewords and multiple-strength Reed-Solomon outer codewords, the Reed-Solomon outer codewords including weak strength, mid-strength, and strong strength. The strength of the codewords can be varied by changing at least one of the code length N, data length K, parity length R, symbol size S and code rate K/N.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: Data is read from a track of a magnetic recording medium via multiple read transducers located at different positions on a read head. The multiple read transducers are substantially positioned over the track when reading the track. The multiple read transducers have different design characteristics manifesting in differences in at least one of magnetic and electrical behavior of the multiple read transducers. One or more signals originating from the multiple read transducers are combined to assist in decoding the data.

Abstract: Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.

Abstract: A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

Abstract: An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.